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| 1 // Copyright (c) 2013, the Dart project authors. Please see the AUTHORS file | 1 // Copyright (c) 2013, the Dart project authors. Please see the AUTHORS file |
| 2 // for details. All rights reserved. Use of this source code is governed by a | 2 // for details. All rights reserved. Use of this source code is governed by a |
| 3 // BSD-style license that can be found in the LICENSE file. | 3 // BSD-style license that can be found in the LICENSE file. |
| 4 // | 4 // |
| 5 // This is forked from Dart revision df52deea9f25690eb8b66c5995da92b70f7ac1fe | 5 // This is forked from Dart revision df52deea9f25690eb8b66c5995da92b70f7ac1fe |
| 6 // Please update the (git) revision if we merge changes from Dart. | 6 // Please update the (git) revision if we merge changes from Dart. |
| 7 // https://code.google.com/p/dart/wiki/GettingTheSource | 7 // https://code.google.com/p/dart/wiki/GettingTheSource |
| 8 | 8 |
| 9 #include "vm/globals.h" // NOLINT | 9 #include "vm/globals.h" // NOLINT |
| 10 #if defined(TARGET_ARCH_ARM) | 10 #if defined(TARGET_ARCH_ARM) |
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| 694 ASSERT(cond != kNoCondition); | 694 ASSERT(cond != kNoCondition); |
| 695 int32_t encoding = (static_cast<int32_t>(cond) << kConditionShift) | | 695 int32_t encoding = (static_cast<int32_t>(cond) << kConditionShift) | |
| 696 B27 | B26 | B25 | | 696 B27 | B26 | B25 | |
| 697 (i*B21) | | 697 (i*B21) | |
| 698 (static_cast<int32_t>(rt)*B12) | B11 | B9 | B8 | | 698 (static_cast<int32_t>(rt)*B12) | B11 | B9 | B8 | |
| 699 ((static_cast<int32_t>(dn) >> 4)*B7) | | 699 ((static_cast<int32_t>(dn) >> 4)*B7) | |
| 700 ((static_cast<int32_t>(dn) & 0xf)*B16) | B4; | 700 ((static_cast<int32_t>(dn) & 0xf)*B16) | B4; |
| 701 Emit(encoding); | 701 Emit(encoding); |
| 702 } | 702 } |
| 703 | 703 |
| 704 | 704 #if 0 |
| 705 // Moved to ARM32::AssemblerARM32::vmovdrr(). |
| 705 void Assembler::vmovdrr(DRegister dm, Register rt, Register rt2, | 706 void Assembler::vmovdrr(DRegister dm, Register rt, Register rt2, |
| 706 Condition cond) { | 707 Condition cond) { |
| 707 ASSERT(TargetCPUFeatures::vfp_supported()); | 708 ASSERT(TargetCPUFeatures::vfp_supported()); |
| 708 ASSERT(dm != kNoDRegister); | 709 ASSERT(dm != kNoDRegister); |
| 709 ASSERT(rt != kNoRegister); | 710 ASSERT(rt != kNoRegister); |
| 710 ASSERT(rt != SP); | 711 ASSERT(rt != SP); |
| 711 ASSERT(rt != PC); | 712 ASSERT(rt != PC); |
| 712 ASSERT(rt2 != kNoRegister); | 713 ASSERT(rt2 != kNoRegister); |
| 713 ASSERT(rt2 != SP); | 714 ASSERT(rt2 != SP); |
| 714 ASSERT(rt2 != PC); | 715 ASSERT(rt2 != PC); |
| 715 ASSERT(cond != kNoCondition); | 716 ASSERT(cond != kNoCondition); |
| 716 int32_t encoding = (static_cast<int32_t>(cond) << kConditionShift) | | 717 int32_t encoding = (static_cast<int32_t>(cond) << kConditionShift) | |
| 717 B27 | B26 | B22 | | 718 B27 | B26 | B22 | |
| 718 (static_cast<int32_t>(rt2)*B16) | | 719 (static_cast<int32_t>(rt2)*B16) | |
| 719 (static_cast<int32_t>(rt)*B12) | B11 | B9 | B8 | | 720 (static_cast<int32_t>(rt)*B12) | B11 | B9 | B8 | |
| 720 ((static_cast<int32_t>(dm) >> 4)*B5) | B4 | | 721 ((static_cast<int32_t>(dm) >> 4)*B5) | B4 | |
| 721 (static_cast<int32_t>(dm) & 0xf); | 722 (static_cast<int32_t>(dm) & 0xf); |
| 722 Emit(encoding); | 723 Emit(encoding); |
| 723 } | 724 } |
| 724 | 725 |
| 725 | 726 // Moved to ARM32::AssemblerARM32::vmovrrd(). |
| 726 void Assembler::vmovrrd(Register rt, Register rt2, DRegister dm, | 727 void Assembler::vmovrrd(Register rt, Register rt2, DRegister dm, |
| 727 Condition cond) { | 728 Condition cond) { |
| 728 ASSERT(TargetCPUFeatures::vfp_supported()); | 729 ASSERT(TargetCPUFeatures::vfp_supported()); |
| 729 ASSERT(dm != kNoDRegister); | 730 ASSERT(dm != kNoDRegister); |
| 730 ASSERT(rt != kNoRegister); | 731 ASSERT(rt != kNoRegister); |
| 731 ASSERT(rt != SP); | 732 ASSERT(rt != SP); |
| 732 ASSERT(rt != PC); | 733 ASSERT(rt != PC); |
| 733 ASSERT(rt2 != kNoRegister); | 734 ASSERT(rt2 != kNoRegister); |
| 734 ASSERT(rt2 != SP); | 735 ASSERT(rt2 != SP); |
| 735 ASSERT(rt2 != PC); | 736 ASSERT(rt2 != PC); |
| 736 ASSERT(rt != rt2); | 737 ASSERT(rt != rt2); |
| 737 ASSERT(cond != kNoCondition); | 738 ASSERT(cond != kNoCondition); |
| 738 int32_t encoding = (static_cast<int32_t>(cond) << kConditionShift) | | 739 int32_t encoding = (static_cast<int32_t>(cond) << kConditionShift) | |
| 739 B27 | B26 | B22 | B20 | | 740 B27 | B26 | B22 | B20 | |
| 740 (static_cast<int32_t>(rt2)*B16) | | 741 (static_cast<int32_t>(rt2)*B16) | |
| 741 (static_cast<int32_t>(rt)*B12) | B11 | B9 | B8 | | 742 (static_cast<int32_t>(rt)*B12) | B11 | B9 | B8 | |
| 742 ((static_cast<int32_t>(dm) >> 4)*B5) | B4 | | 743 ((static_cast<int32_t>(dm) >> 4)*B5) | B4 | |
| 743 (static_cast<int32_t>(dm) & 0xf); | 744 (static_cast<int32_t>(dm) & 0xf); |
| 744 Emit(encoding); | 745 Emit(encoding); |
| 745 } | 746 } |
| 746 | 747 |
| 747 #if 0 | |
| 748 // Moved to ARM32::AssemblerARM32::vldrs() | 748 // Moved to ARM32::AssemblerARM32::vldrs() |
| 749 void Assembler::vldrs(SRegister sd, Address ad, Condition cond) { | 749 void Assembler::vldrs(SRegister sd, Address ad, Condition cond) { |
| 750 ASSERT(TargetCPUFeatures::vfp_supported()); | 750 ASSERT(TargetCPUFeatures::vfp_supported()); |
| 751 ASSERT(sd != kNoSRegister); | 751 ASSERT(sd != kNoSRegister); |
| 752 ASSERT(cond != kNoCondition); | 752 ASSERT(cond != kNoCondition); |
| 753 int32_t encoding = (static_cast<int32_t>(cond) << kConditionShift) | | 753 int32_t encoding = (static_cast<int32_t>(cond) << kConditionShift) | |
| 754 B27 | B26 | B24 | B20 | | 754 B27 | B26 | B24 | B20 | |
| 755 ((static_cast<int32_t>(sd) & 1)*B22) | | 755 ((static_cast<int32_t>(sd) & 1)*B22) | |
| 756 ((static_cast<int32_t>(sd) >> 1)*B12) | | 756 ((static_cast<int32_t>(sd) >> 1)*B12) | |
| 757 B11 | B9 | ad.vencoding(); | 757 B11 | B9 | ad.vencoding(); |
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| 3686 | 3686 |
| 3687 | 3687 |
| 3688 const char* Assembler::FpuRegisterName(FpuRegister reg) { | 3688 const char* Assembler::FpuRegisterName(FpuRegister reg) { |
| 3689 ASSERT((0 <= reg) && (reg < kNumberOfFpuRegisters)); | 3689 ASSERT((0 <= reg) && (reg < kNumberOfFpuRegisters)); |
| 3690 return fpu_reg_names[reg]; | 3690 return fpu_reg_names[reg]; |
| 3691 } | 3691 } |
| 3692 | 3692 |
| 3693 } // namespace dart | 3693 } // namespace dart |
| 3694 | 3694 |
| 3695 #endif // defined TARGET_ARCH_ARM | 3695 #endif // defined TARGET_ARCH_ARM |
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