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1 //===- subzero/src/IceTargetLoweringX86BaseImpl.h - x86 lowering -*- C++ -*-==// | 1 //===- subzero/src/IceTargetLoweringX86BaseImpl.h - x86 lowering -*- C++ -*-==// |
2 // | 2 // |
3 // The Subzero Code Generator | 3 // The Subzero Code Generator |
4 // | 4 // |
5 // This file is distributed under the University of Illinois Open Source | 5 // This file is distributed under the University of Illinois Open Source |
6 // License. See LICENSE.TXT for details. | 6 // License. See LICENSE.TXT for details. |
7 // | 7 // |
8 //===----------------------------------------------------------------------===// | 8 //===----------------------------------------------------------------------===// |
9 /// | 9 /// |
10 /// \file | 10 /// \file |
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372 (Func->getContext()->getFlags().getTargetInstructionSet() - | 372 (Func->getContext()->getFlags().getTargetInstructionSet() - |
373 TargetInstructionSet::X86InstructionSet_Begin) + | 373 TargetInstructionSet::X86InstructionSet_Begin) + |
374 Traits::InstructionSet::Begin); | 374 Traits::InstructionSet::Begin); |
375 } | 375 } |
376 } | 376 } |
377 | 377 |
378 template <typename TraitsType> | 378 template <typename TraitsType> |
379 void TargetX86Base<TraitsType>::staticInit(GlobalContext *Ctx) { | 379 void TargetX86Base<TraitsType>::staticInit(GlobalContext *Ctx) { |
380 Traits::initRegisterSet(Ctx->getFlags(), &TypeToRegisterSet, | 380 Traits::initRegisterSet(Ctx->getFlags(), &TypeToRegisterSet, |
381 &RegisterAliases); | 381 &RegisterAliases); |
| 382 for (size_t i = 0; i < TypeToRegisterSet.size(); ++i) |
| 383 TypeToRegisterSetUnfiltered[i] = TypeToRegisterSet[i]; |
382 filterTypeToRegisterSet(Ctx, Traits::RegisterSet::Reg_NUM, | 384 filterTypeToRegisterSet(Ctx, Traits::RegisterSet::Reg_NUM, |
383 TypeToRegisterSet.data(), TypeToRegisterSet.size(), | 385 TypeToRegisterSet.data(), TypeToRegisterSet.size(), |
384 Traits::getRegName, getRegClassName); | 386 Traits::getRegName, getRegClassName); |
385 PcRelFixup = Traits::FK_PcRel; | 387 PcRelFixup = Traits::FK_PcRel; |
386 AbsFixup = | 388 AbsFixup = |
387 Ctx->getFlags().getUseNonsfi() ? Traits::FK_Gotoff : Traits::FK_Abs; | 389 Ctx->getFlags().getUseNonsfi() ? Traits::FK_Gotoff : Traits::FK_Abs; |
388 } | 390 } |
389 | 391 |
390 template <typename TraitsType> void TargetX86Base<TraitsType>::translateO2() { | 392 template <typename TraitsType> void TargetX86Base<TraitsType>::translateO2() { |
391 TimerMarker T(TimerStack::TT_O2, Func); | 393 TimerMarker T(TimerStack::TT_O2, Func); |
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1938 // t3:eax = b.lo | 1940 // t3:eax = b.lo |
1939 // t4.hi:edx,t4.lo:eax = t3:eax *(mul) c.lo | 1941 // t4.hi:edx,t4.lo:eax = t3:eax *(mul) c.lo |
1940 // a.lo = t4.lo | 1942 // a.lo = t4.lo |
1941 // t4.hi += t1 | 1943 // t4.hi += t1 |
1942 // t4.hi += t2 | 1944 // t4.hi += t2 |
1943 // a.hi = t4.hi | 1945 // a.hi = t4.hi |
1944 // The mul instruction cannot take an immediate operand. | 1946 // The mul instruction cannot take an immediate operand. |
1945 Src1Lo = legalize(Src1Lo, Legal_Reg | Legal_Mem); | 1947 Src1Lo = legalize(Src1Lo, Legal_Reg | Legal_Mem); |
1946 _mov(T_1, Src0Hi); | 1948 _mov(T_1, Src0Hi); |
1947 _imul(T_1, Src1Lo); | 1949 _imul(T_1, Src1Lo); |
1948 _mov(T_2, Src1Hi); | |
1949 _imul(T_2, Src0Lo); | |
1950 _mov(T_3, Src0Lo, Traits::RegisterSet::Reg_eax); | 1950 _mov(T_3, Src0Lo, Traits::RegisterSet::Reg_eax); |
1951 _mul(T_4Lo, T_3, Src1Lo); | 1951 _mul(T_4Lo, T_3, Src1Lo); |
1952 // The mul instruction produces two dest variables, edx:eax. We create a | 1952 // The mul instruction produces two dest variables, edx:eax. We create a |
1953 // fake definition of edx to account for this. | 1953 // fake definition of edx to account for this. |
1954 Context.insert<InstFakeDef>(T_4Hi, T_4Lo); | 1954 Context.insert<InstFakeDef>(T_4Hi, T_4Lo); |
1955 _mov(DestLo, T_4Lo); | 1955 _mov(DestLo, T_4Lo); |
1956 _add(T_4Hi, T_1); | 1956 _add(T_4Hi, T_1); |
| 1957 _mov(T_2, Src1Hi); |
| 1958 _imul(T_2, Src0Lo); |
1957 _add(T_4Hi, T_2); | 1959 _add(T_4Hi, T_2); |
1958 _mov(DestHi, T_4Hi); | 1960 _mov(DestHi, T_4Hi); |
1959 } break; | 1961 } break; |
1960 case InstArithmetic::Shl: | 1962 case InstArithmetic::Shl: |
1961 case InstArithmetic::Lshr: | 1963 case InstArithmetic::Lshr: |
1962 case InstArithmetic::Ashr: | 1964 case InstArithmetic::Ashr: |
1963 lowerShift64(Inst->getOp(), Src0Lo, Src0Hi, Src1Lo, DestLo, DestHi); | 1965 lowerShift64(Inst->getOp(), Src0Lo, Src0Hi, Src1Lo, DestLo, DestHi); |
1964 break; | 1966 break; |
1965 case InstArithmetic::Fadd: | 1967 case InstArithmetic::Fadd: |
1966 case InstArithmetic::Fsub: | 1968 case InstArithmetic::Fsub: |
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5794 void TargetX86Base<TraitsType>::lowerStore(const InstStore *Inst) { | 5796 void TargetX86Base<TraitsType>::lowerStore(const InstStore *Inst) { |
5795 Operand *Value = Inst->getData(); | 5797 Operand *Value = Inst->getData(); |
5796 Operand *Addr = Inst->getAddr(); | 5798 Operand *Addr = Inst->getAddr(); |
5797 X86OperandMem *NewAddr = formMemoryOperand(Addr, Value->getType()); | 5799 X86OperandMem *NewAddr = formMemoryOperand(Addr, Value->getType()); |
5798 doMockBoundsCheck(NewAddr); | 5800 doMockBoundsCheck(NewAddr); |
5799 Type Ty = NewAddr->getType(); | 5801 Type Ty = NewAddr->getType(); |
5800 | 5802 |
5801 if (!Traits::Is64Bit && Ty == IceType_i64) { | 5803 if (!Traits::Is64Bit && Ty == IceType_i64) { |
5802 Value = legalizeUndef(Value); | 5804 Value = legalizeUndef(Value); |
5803 Operand *ValueHi = legalize(hiOperand(Value), Legal_Reg | Legal_Imm); | 5805 Operand *ValueHi = legalize(hiOperand(Value), Legal_Reg | Legal_Imm); |
| 5806 _store(ValueHi, llvm::cast<X86OperandMem>(hiOperand(NewAddr))); |
5804 Operand *ValueLo = legalize(loOperand(Value), Legal_Reg | Legal_Imm); | 5807 Operand *ValueLo = legalize(loOperand(Value), Legal_Reg | Legal_Imm); |
5805 _store(ValueHi, llvm::cast<X86OperandMem>(hiOperand(NewAddr))); | |
5806 _store(ValueLo, llvm::cast<X86OperandMem>(loOperand(NewAddr))); | 5808 _store(ValueLo, llvm::cast<X86OperandMem>(loOperand(NewAddr))); |
5807 } else if (isVectorType(Ty)) { | 5809 } else if (isVectorType(Ty)) { |
5808 _storep(legalizeToReg(Value), NewAddr); | 5810 _storep(legalizeToReg(Value), NewAddr); |
5809 } else { | 5811 } else { |
5810 Value = legalize(Value, Legal_Reg | Legal_Imm); | 5812 Value = legalize(Value, Legal_Reg | Legal_Imm); |
5811 _store(Value, NewAddr); | 5813 _store(Value, NewAddr); |
5812 } | 5814 } |
5813 } | 5815 } |
5814 | 5816 |
5815 template <typename TraitsType> | 5817 template <typename TraitsType> |
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7455 emitGlobal(*Var, SectionSuffix); | 7457 emitGlobal(*Var, SectionSuffix); |
7456 } | 7458 } |
7457 } | 7459 } |
7458 } break; | 7460 } break; |
7459 } | 7461 } |
7460 } | 7462 } |
7461 } // end of namespace X86NAMESPACE | 7463 } // end of namespace X86NAMESPACE |
7462 } // end of namespace Ice | 7464 } // end of namespace Ice |
7463 | 7465 |
7464 #endif // SUBZERO_SRC_ICETARGETLOWERINGX86BASEIMPL_H | 7466 #endif // SUBZERO_SRC_ICETARGETLOWERINGX86BASEIMPL_H |
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