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| 1 //===- subzero/src/IceTargetLoweringMIPS32.h - MIPS32 lowering ---*- C++-*-===// | 1 //===- subzero/src/IceTargetLoweringMIPS32.h - MIPS32 lowering ---*- C++-*-===// |
| 2 // | 2 // |
| 3 // The Subzero Code Generator | 3 // The Subzero Code Generator |
| 4 // | 4 // |
| 5 // This file is distributed under the University of Illinois Open Source | 5 // This file is distributed under the University of Illinois Open Source |
| 6 // License. See LICENSE.TXT for details. | 6 // License. See LICENSE.TXT for details. |
| 7 // | 7 // |
| 8 //===----------------------------------------------------------------------===// | 8 //===----------------------------------------------------------------------===// |
| 9 /// | 9 /// |
| 10 /// \file | 10 /// \file |
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| 50 Variable *getPhysicalRegister(SizeT RegNum, Type Ty = IceType_void) override; | 50 Variable *getPhysicalRegister(SizeT RegNum, Type Ty = IceType_void) override; |
| 51 IceString getRegName(SizeT RegNum, Type Ty) const override; | 51 IceString getRegName(SizeT RegNum, Type Ty) const override; |
| 52 llvm::SmallBitVector getRegisterSet(RegSetMask Include, | 52 llvm::SmallBitVector getRegisterSet(RegSetMask Include, |
| 53 RegSetMask Exclude) const override; | 53 RegSetMask Exclude) const override; |
| 54 const llvm::SmallBitVector & | 54 const llvm::SmallBitVector & |
| 55 getRegistersForVariable(const Variable *Var) const override { | 55 getRegistersForVariable(const Variable *Var) const override { |
| 56 RegClass RC = Var->getRegClass(); | 56 RegClass RC = Var->getRegClass(); |
| 57 assert(RC < RC_Target); | 57 assert(RC < RC_Target); |
| 58 return TypeToRegisterSet[RC]; | 58 return TypeToRegisterSet[RC]; |
| 59 } | 59 } |
| 60 const llvm::SmallBitVector & |
| 61 getAllRegistersForVariable(const Variable *Var) const override { |
| 62 RegClass RC = Var->getRegClass(); |
| 63 assert(RC < RC_Target); |
| 64 return TypeToRegisterSetUnfiltered[RC]; |
| 65 } |
| 60 const llvm::SmallBitVector &getAliasesForRegister(SizeT Reg) const override { | 66 const llvm::SmallBitVector &getAliasesForRegister(SizeT Reg) const override { |
| 61 return RegisterAliases[Reg]; | 67 return RegisterAliases[Reg]; |
| 62 } | 68 } |
| 63 bool hasFramePointer() const override { return UsesFramePointer; } | 69 bool hasFramePointer() const override { return UsesFramePointer; } |
| 64 void setHasFramePointer() override { UsesFramePointer = true; } | 70 void setHasFramePointer() override { UsesFramePointer = true; } |
| 65 SizeT getStackReg() const override { return RegMIPS32::Reg_SP; } | 71 SizeT getStackReg() const override { return RegMIPS32::Reg_SP; } |
| 66 SizeT getFrameReg() const override { return RegMIPS32::Reg_FP; } | 72 SizeT getFrameReg() const override { return RegMIPS32::Reg_FP; } |
| 67 SizeT getFrameOrStackReg() const override { | 73 SizeT getFrameOrStackReg() const override { |
| 68 return UsesFramePointer ? getFrameReg() : getStackReg(); | 74 return UsesFramePointer ? getFrameReg() : getStackReg(); |
| 69 } | 75 } |
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| 256 void randomlyInsertNop(float Probability, | 262 void randomlyInsertNop(float Probability, |
| 257 RandomNumberGenerator &RNG) override; | 263 RandomNumberGenerator &RNG) override; |
| 258 void | 264 void |
| 259 makeRandomRegisterPermutation(llvm::SmallVectorImpl<int32_t> &Permutation, | 265 makeRandomRegisterPermutation(llvm::SmallVectorImpl<int32_t> &Permutation, |
| 260 const llvm::SmallBitVector &ExcludeRegisters, | 266 const llvm::SmallBitVector &ExcludeRegisters, |
| 261 uint64_t Salt) const override; | 267 uint64_t Salt) const override; |
| 262 | 268 |
| 263 bool UsesFramePointer = false; | 269 bool UsesFramePointer = false; |
| 264 bool NeedsStackAlignment = false; | 270 bool NeedsStackAlignment = false; |
| 265 static llvm::SmallBitVector TypeToRegisterSet[RCMIPS32_NUM]; | 271 static llvm::SmallBitVector TypeToRegisterSet[RCMIPS32_NUM]; |
| 272 static llvm::SmallBitVector TypeToRegisterSetUnfiltered[RCMIPS32_NUM]; |
| 266 static llvm::SmallBitVector RegisterAliases[RegMIPS32::Reg_NUM]; | 273 static llvm::SmallBitVector RegisterAliases[RegMIPS32::Reg_NUM]; |
| 267 llvm::SmallBitVector RegsUsed; | 274 llvm::SmallBitVector RegsUsed; |
| 268 VarList PhysicalRegisters[IceType_NUM]; | 275 VarList PhysicalRegisters[IceType_NUM]; |
| 269 | 276 |
| 270 private: | 277 private: |
| 271 ENABLE_MAKE_UNIQUE; | 278 ENABLE_MAKE_UNIQUE; |
| 272 }; | 279 }; |
| 273 | 280 |
| 274 class TargetDataMIPS32 final : public TargetDataLowering { | 281 class TargetDataMIPS32 final : public TargetDataLowering { |
| 275 TargetDataMIPS32() = delete; | 282 TargetDataMIPS32() = delete; |
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| 310 explicit TargetHeaderMIPS32(GlobalContext *Ctx); | 317 explicit TargetHeaderMIPS32(GlobalContext *Ctx); |
| 311 | 318 |
| 312 private: | 319 private: |
| 313 ~TargetHeaderMIPS32() = default; | 320 ~TargetHeaderMIPS32() = default; |
| 314 }; | 321 }; |
| 315 | 322 |
| 316 } // end of namespace MIPS32 | 323 } // end of namespace MIPS32 |
| 317 } // end of namespace Ice | 324 } // end of namespace Ice |
| 318 | 325 |
| 319 #endif // SUBZERO_SRC_ICETARGETLOWERINGMIPS32_H | 326 #endif // SUBZERO_SRC_ICETARGETLOWERINGMIPS32_H |
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