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1 //===- subzero/src/IceTargetLoweringARM32.h - ARM32 lowering ----*- C++ -*-===// | 1 //===- subzero/src/IceTargetLoweringARM32.h - ARM32 lowering ----*- C++ -*-===// |
2 // | 2 // |
3 // The Subzero Code Generator | 3 // The Subzero Code Generator |
4 // | 4 // |
5 // This file is distributed under the University of Illinois Open Source | 5 // This file is distributed under the University of Illinois Open Source |
6 // License. See LICENSE.TXT for details. | 6 // License. See LICENSE.TXT for details. |
7 // | 7 // |
8 //===----------------------------------------------------------------------===// | 8 //===----------------------------------------------------------------------===// |
9 /// | 9 /// |
10 /// \file | 10 /// \file |
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81 Variable *getPhysicalRegister(SizeT RegNum, Type Ty = IceType_void) override; | 81 Variable *getPhysicalRegister(SizeT RegNum, Type Ty = IceType_void) override; |
82 IceString getRegName(SizeT RegNum, Type Ty) const override; | 82 IceString getRegName(SizeT RegNum, Type Ty) const override; |
83 llvm::SmallBitVector getRegisterSet(RegSetMask Include, | 83 llvm::SmallBitVector getRegisterSet(RegSetMask Include, |
84 RegSetMask Exclude) const override; | 84 RegSetMask Exclude) const override; |
85 const llvm::SmallBitVector & | 85 const llvm::SmallBitVector & |
86 getRegistersForVariable(const Variable *Var) const override { | 86 getRegistersForVariable(const Variable *Var) const override { |
87 RegClass RC = Var->getRegClass(); | 87 RegClass RC = Var->getRegClass(); |
88 assert(RC < RC_Target); | 88 assert(RC < RC_Target); |
89 return TypeToRegisterSet[RC]; | 89 return TypeToRegisterSet[RC]; |
90 } | 90 } |
| 91 const llvm::SmallBitVector & |
| 92 getAllRegistersForVariable(const Variable *Var) const override { |
| 93 RegClass RC = Var->getRegClass(); |
| 94 assert(RC < RC_Target); |
| 95 return TypeToRegisterSetUnfiltered[RC]; |
| 96 } |
91 const llvm::SmallBitVector &getAliasesForRegister(SizeT Reg) const override { | 97 const llvm::SmallBitVector &getAliasesForRegister(SizeT Reg) const override { |
92 return RegisterAliases[Reg]; | 98 return RegisterAliases[Reg]; |
93 } | 99 } |
94 bool hasFramePointer() const override { return UsesFramePointer; } | 100 bool hasFramePointer() const override { return UsesFramePointer; } |
95 void setHasFramePointer() override { UsesFramePointer = true; } | 101 void setHasFramePointer() override { UsesFramePointer = true; } |
96 SizeT getStackReg() const override { return RegARM32::Reg_sp; } | 102 SizeT getStackReg() const override { return RegARM32::Reg_sp; } |
97 SizeT getFrameReg() const override { return RegARM32::Reg_fp; } | 103 SizeT getFrameReg() const override { return RegARM32::Reg_fp; } |
98 SizeT getFrameOrStackReg() const override { | 104 SizeT getFrameOrStackReg() const override { |
99 return UsesFramePointer ? getFrameReg() : getStackReg(); | 105 return UsesFramePointer ? getFrameReg() : getStackReg(); |
100 } | 106 } |
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1013 bool UsesFramePointer = false; | 1019 bool UsesFramePointer = false; |
1014 bool NeedsStackAlignment = false; | 1020 bool NeedsStackAlignment = false; |
1015 bool MaybeLeafFunc = true; | 1021 bool MaybeLeafFunc = true; |
1016 size_t SpillAreaSizeBytes = 0; | 1022 size_t SpillAreaSizeBytes = 0; |
1017 size_t FixedAllocaSizeBytes = 0; | 1023 size_t FixedAllocaSizeBytes = 0; |
1018 size_t FixedAllocaAlignBytes = 0; | 1024 size_t FixedAllocaAlignBytes = 0; |
1019 bool PrologEmitsFixedAllocas = false; | 1025 bool PrologEmitsFixedAllocas = false; |
1020 uint32_t MaxOutArgsSizeBytes = 0; | 1026 uint32_t MaxOutArgsSizeBytes = 0; |
1021 // TODO(jpp): std::array instead of array. | 1027 // TODO(jpp): std::array instead of array. |
1022 static llvm::SmallBitVector TypeToRegisterSet[RegARM32::RCARM32_NUM]; | 1028 static llvm::SmallBitVector TypeToRegisterSet[RegARM32::RCARM32_NUM]; |
| 1029 static llvm::SmallBitVector |
| 1030 TypeToRegisterSetUnfiltered[RegARM32::RCARM32_NUM]; |
1023 static llvm::SmallBitVector RegisterAliases[RegARM32::Reg_NUM]; | 1031 static llvm::SmallBitVector RegisterAliases[RegARM32::Reg_NUM]; |
1024 llvm::SmallBitVector RegsUsed; | 1032 llvm::SmallBitVector RegsUsed; |
1025 VarList PhysicalRegisters[IceType_NUM]; | 1033 VarList PhysicalRegisters[IceType_NUM]; |
1026 VarList PreservedGPRs; | 1034 VarList PreservedGPRs; |
1027 VarList PreservedSRegs; | 1035 VarList PreservedSRegs; |
1028 | 1036 |
1029 /// Helper class that understands the Calling Convention and register | 1037 /// Helper class that understands the Calling Convention and register |
1030 /// assignments. The first few integer type parameters can use r0-r3, | 1038 /// assignments. The first few integer type parameters can use r0-r3, |
1031 /// regardless of their position relative to the floating-point/vector | 1039 /// regardless of their position relative to the floating-point/vector |
1032 /// arguments in the argument list. Floating-point and vector arguments | 1040 /// arguments in the argument list. Floating-point and vector arguments |
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1208 private: | 1216 private: |
1209 ~TargetHeaderARM32() = default; | 1217 ~TargetHeaderARM32() = default; |
1210 | 1218 |
1211 TargetARM32Features CPUFeatures; | 1219 TargetARM32Features CPUFeatures; |
1212 }; | 1220 }; |
1213 | 1221 |
1214 } // end of namespace ARM32 | 1222 } // end of namespace ARM32 |
1215 } // end of namespace Ice | 1223 } // end of namespace Ice |
1216 | 1224 |
1217 #endif // SUBZERO_SRC_ICETARGETLOWERINGARM32_H | 1225 #endif // SUBZERO_SRC_ICETARGETLOWERINGARM32_H |
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