ARM32 vorr lowering

src/IceTargetLoweringARM32.cpp

 //===- subzero/src/IceTargetLoweringARM32.cpp - ARM32 lowering ------------===//
 //
 //                        The Subzero Code Generator
 //
 // This file is distributed under the University of Illinois Open Source
 // License. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
 ///
 /// \file
@@ skipping 2790 matching lines @@
     switch (Instr->getOp()) {
     default:
       UnimplementedLoweringError(this, Instr);
       return;
     // Explicitly whitelist vector instructions we have implemented/enabled.
     case InstArithmetic::Fadd:
     case InstArithmetic::Add:
     case InstArithmetic::Fsub:
     case InstArithmetic::Sub:
     case InstArithmetic::And:
+    case InstArithmetic::Or:
       break;
     }
   }
 
   Variable *T = makeReg(DestTy);
 
   // * Handle div/rem separately. They require a non-legalized Src1 to inspect
   // whether or not Src1 is a non-zero constant. Once legalized it is more
   // difficult to determine (constant may be moved to a register).
   // * Handle floating point arithmetic separately: they require Src1 to be
@@ skipping 140 matching lines @@
       _vand(T, Src0R, Src1R);
     } else {
       Operand *Src1RF = Srcs.src1RF(this);
       _and(T, Src0R, Src1RF);
     }
     _mov(Dest, T);
     return;
   }
   case InstArithmetic::Or: {
     Variable *Src0R = Srcs.src0R(this);
-    Operand *Src1RF = Srcs.src1RF(this);
-    _orr(T, Src0R, Src1RF);
+    if (isVectorType(DestTy)) {
+      Variable *Src1R = legalizeToReg(Src1);
+      _vorr(T, Src0R, Src1R);
+    } else {
+      Operand *Src1RF = Srcs.src1RF(this);
+      _orr(T, Src0R, Src1RF);
+    }
     _mov(Dest, T);
     return;
   }
   case InstArithmetic::Xor: {
     Variable *Src0R = Srcs.src0R(this);
     Operand *Src1RF = Srcs.src1RF(this);
     _eor(T, Src0R, Src1RF);
     _mov(Dest, T);
     return;
   }
@@ skipping 3510 matching lines @@
   // Technically R9 is used for TLS with Sandboxing, and we reserve it.
   // However, for compatibility with current NaCl LLVM, don't claim that.
   Str << ".eabi_attribute 14, 3   @ Tag_ABI_PCS_R9_use: Not used\n";
 }
 
 llvm::SmallBitVector TargetARM32::TypeToRegisterSet[RegARM32::RCARM32_NUM];
 llvm::SmallBitVector TargetARM32::RegisterAliases[RegARM32::Reg_NUM];
 
 } // end of namespace ARM32
 } // end of namespace Ice