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1 //===- subzero/src/IceTargetLoweringARM32.h - ARM32 lowering ----*- C++ -*-===// | 1 //===- subzero/src/IceTargetLoweringARM32.h - ARM32 lowering ----*- C++ -*-===// |
2 // | 2 // |
3 // The Subzero Code Generator | 3 // The Subzero Code Generator |
4 // | 4 // |
5 // This file is distributed under the University of Illinois Open Source | 5 // This file is distributed under the University of Illinois Open Source |
6 // License. See LICENSE.TXT for details. | 6 // License. See LICENSE.TXT for details. |
7 // | 7 // |
8 //===----------------------------------------------------------------------===// | 8 //===----------------------------------------------------------------------===// |
9 /// | 9 /// |
10 /// \file | 10 /// \file |
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765 void _vabs(Variable *Dest, Variable *Src, | 765 void _vabs(Variable *Dest, Variable *Src, |
766 CondARM32::Cond Pred = CondARM32::AL) { | 766 CondARM32::Cond Pred = CondARM32::AL) { |
767 Context.insert<InstARM32Vabs>(Dest, Src, Pred); | 767 Context.insert<InstARM32Vabs>(Dest, Src, Pred); |
768 } | 768 } |
769 void _vadd(Variable *Dest, Variable *Src0, Variable *Src1) { | 769 void _vadd(Variable *Dest, Variable *Src0, Variable *Src1) { |
770 Context.insert<InstARM32Vadd>(Dest, Src0, Src1); | 770 Context.insert<InstARM32Vadd>(Dest, Src0, Src1); |
771 } | 771 } |
772 void _vand(Variable *Dest, Variable *Src0, Variable *Src1) { | 772 void _vand(Variable *Dest, Variable *Src0, Variable *Src1) { |
773 Context.insert<InstARM32Vand>(Dest, Src0, Src1); | 773 Context.insert<InstARM32Vand>(Dest, Src0, Src1); |
774 } | 774 } |
775 void _vorr(Variable *Dest, Variable *Src0, Variable *Src1) { | |
Jim Stichnoth
2016/01/27 22:38:05
This should probably be inserted alphabetically.
Eric Holk
2016/01/27 22:51:47
Done.
| |
776 Context.insert<InstARM32Vorr>(Dest, Src0, Src1); | |
777 } | |
775 void _vcvt(Variable *Dest, Variable *Src, InstARM32Vcvt::VcvtVariant Variant, | 778 void _vcvt(Variable *Dest, Variable *Src, InstARM32Vcvt::VcvtVariant Variant, |
776 CondARM32::Cond Pred = CondARM32::AL) { | 779 CondARM32::Cond Pred = CondARM32::AL) { |
777 Context.insert<InstARM32Vcvt>(Dest, Src, Variant, Pred); | 780 Context.insert<InstARM32Vcvt>(Dest, Src, Variant, Pred); |
778 } | 781 } |
779 void _vdiv(Variable *Dest, Variable *Src0, Variable *Src1) { | 782 void _vdiv(Variable *Dest, Variable *Src0, Variable *Src1) { |
780 Context.insert<InstARM32Vdiv>(Dest, Src0, Src1); | 783 Context.insert<InstARM32Vdiv>(Dest, Src0, Src1); |
781 } | 784 } |
782 void _vcmp(Variable *Src0, Variable *Src1, | 785 void _vcmp(Variable *Src0, Variable *Src1, |
783 CondARM32::Cond Pred = CondARM32::AL) { | 786 CondARM32::Cond Pred = CondARM32::AL) { |
784 Context.insert<InstARM32Vcmp>(Src0, Src1, Pred); | 787 Context.insert<InstARM32Vcmp>(Src0, Src1, Pred); |
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1205 private: | 1208 private: |
1206 ~TargetHeaderARM32() = default; | 1209 ~TargetHeaderARM32() = default; |
1207 | 1210 |
1208 TargetARM32Features CPUFeatures; | 1211 TargetARM32Features CPUFeatures; |
1209 }; | 1212 }; |
1210 | 1213 |
1211 } // end of namespace ARM32 | 1214 } // end of namespace ARM32 |
1212 } // end of namespace Ice | 1215 } // end of namespace Ice |
1213 | 1216 |
1214 #endif // SUBZERO_SRC_ICETARGETLOWERINGARM32_H | 1217 #endif // SUBZERO_SRC_ICETARGETLOWERINGARM32_H |
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