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Issue 16381006: Change PC for OSR entries to point to something more sensible (i.e. the first UnknownOsrValue), rem… (Closed) Base URL: https://v8.googlecode.com/svn/branches/bleeding_edge
Patch Set: Add --always-osr flag. Created 7 years, 5 months ago
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1 // Copyright 2012 the V8 project authors. All rights reserved. 1 // Copyright 2012 the V8 project authors. All rights reserved.
2 // Redistribution and use in source and binary forms, with or without 2 // Redistribution and use in source and binary forms, with or without
3 // modification, are permitted provided that the following conditions are 3 // modification, are permitted provided that the following conditions are
4 // met: 4 // met:
5 // 5 //
6 // * Redistributions of source code must retain the above copyright 6 // * Redistributions of source code must retain the above copyright
7 // notice, this list of conditions and the following disclaimer. 7 // notice, this list of conditions and the following disclaimer.
8 // * Redistributions in binary form must reproduce the above 8 // * Redistributions in binary form must reproduce the above
9 // copyright notice, this list of conditions and the following 9 // copyright notice, this list of conditions and the following
10 // disclaimer in the documentation and/or other materials provided 10 // disclaimer in the documentation and/or other materials provided
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36 namespace v8 { 36 namespace v8 {
37 namespace internal { 37 namespace internal {
38 38
39 #define DEFINE_COMPILE(type) \ 39 #define DEFINE_COMPILE(type) \
40 void L##type::CompileToNative(LCodeGen* generator) { \ 40 void L##type::CompileToNative(LCodeGen* generator) { \
41 generator->Do##type(this); \ 41 generator->Do##type(this); \
42 } 42 }
43 LITHIUM_CONCRETE_INSTRUCTION_LIST(DEFINE_COMPILE) 43 LITHIUM_CONCRETE_INSTRUCTION_LIST(DEFINE_COMPILE)
44 #undef DEFINE_COMPILE 44 #undef DEFINE_COMPILE
45 45
46 LOsrEntry::LOsrEntry() {
47 for (int i = 0; i < Register::NumAllocatableRegisters(); ++i) {
48 register_spills_[i] = NULL;
49 }
50 for (int i = 0; i < DoubleRegister::NumAllocatableRegisters(); ++i) {
51 double_register_spills_[i] = NULL;
52 }
53 }
54
55
56 void LOsrEntry::MarkSpilledRegister(int allocation_index,
57 LOperand* spill_operand) {
58 ASSERT(spill_operand->IsStackSlot());
59 ASSERT(register_spills_[allocation_index] == NULL);
60 register_spills_[allocation_index] = spill_operand;
61 }
62
63
64 void LOsrEntry::MarkSpilledDoubleRegister(int allocation_index,
65 LOperand* spill_operand) {
66 ASSERT(spill_operand->IsDoubleStackSlot());
67 ASSERT(double_register_spills_[allocation_index] == NULL);
68 double_register_spills_[allocation_index] = spill_operand;
69 }
70
71 46
72 #ifdef DEBUG 47 #ifdef DEBUG
73 void LInstruction::VerifyCall() { 48 void LInstruction::VerifyCall() {
74 // Call instructions can use only fixed registers as temporaries and 49 // Call instructions can use only fixed registers as temporaries and
75 // outputs because all registers are blocked by the calling convention. 50 // outputs because all registers are blocked by the calling convention.
76 // Inputs operands must use a fixed register or use-at-start policy or 51 // Inputs operands must use a fixed register or use-at-start policy or
77 // a non-register policy. 52 // a non-register policy.
78 ASSERT(Output() == NULL || 53 ASSERT(Output() == NULL ||
79 LUnallocated::cast(Output())->HasFixedPolicy() || 54 LUnallocated::cast(Output())->HasFixedPolicy() ||
80 !LUnallocated::cast(Output())->HasRegisterPolicy()); 55 !LUnallocated::cast(Output())->HasRegisterPolicy());
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2813 LInstruction* LChunkBuilder::DoLoadFieldByIndex(HLoadFieldByIndex* instr) { 2788 LInstruction* LChunkBuilder::DoLoadFieldByIndex(HLoadFieldByIndex* instr) {
2814 LOperand* object = UseRegister(instr->object()); 2789 LOperand* object = UseRegister(instr->object());
2815 LOperand* index = UseTempRegister(instr->index()); 2790 LOperand* index = UseTempRegister(instr->index());
2816 return DefineSameAsFirst(new(zone()) LLoadFieldByIndex(object, index)); 2791 return DefineSameAsFirst(new(zone()) LLoadFieldByIndex(object, index));
2817 } 2792 }
2818 2793
2819 2794
2820 } } // namespace v8::internal 2795 } } // namespace v8::internal
2821 2796
2822 #endif // V8_TARGET_ARCH_IA32 2797 #endif // V8_TARGET_ARCH_IA32
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