| Index: src/IceTargetLoweringARM32.cpp
|
| diff --git a/src/IceTargetLoweringARM32.cpp b/src/IceTargetLoweringARM32.cpp
|
| index 5e7bdfd11fc04771f337805164e13b05d1a6ca56..4ce665ee464fb13b6e2d7d2f6d7c246f4eb82337 100644
|
| --- a/src/IceTargetLoweringARM32.cpp
|
| +++ b/src/IceTargetLoweringARM32.cpp
|
| @@ -2805,6 +2805,7 @@ void TargetARM32::lowerArithmetic(const InstArithmetic *Instr) {
|
| // Explicitly whitelist vector instructions we have implemented/enabled.
|
| case InstArithmetic::Fadd:
|
| case InstArithmetic::Add:
|
| + case InstArithmetic::And:
|
| break;
|
| }
|
| }
|
| @@ -2953,8 +2954,13 @@ void TargetARM32::lowerArithmetic(const InstArithmetic *Instr) {
|
| }
|
| }
|
| Variable *Src0R = Srcs.src0R(this);
|
| - Operand *Src1RF = Srcs.src1RF(this);
|
| - _and(T, Src0R, Src1RF);
|
| + if (isVectorType(DestTy)) {
|
| + Variable *Src1R = legalizeToReg(Src1);
|
| + _vand(T, Src0R, Src1R);
|
| + } else {
|
| + Operand *Src1RF = Srcs.src1RF(this);
|
| + _and(T, Src0R, Src1RF);
|
| + }
|
| _mov(Dest, T);
|
| return;
|
| }
|
|
|