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| 1 //===- subzero/src/IceTargetLoweringARM32.h - ARM32 lowering ----*- C++ -*-===// | 1 //===- subzero/src/IceTargetLoweringARM32.h - ARM32 lowering ----*- C++ -*-===// |
| 2 // | 2 // |
| 3 // The Subzero Code Generator | 3 // The Subzero Code Generator |
| 4 // | 4 // |
| 5 // This file is distributed under the University of Illinois Open Source | 5 // This file is distributed under the University of Illinois Open Source |
| 6 // License. See LICENSE.TXT for details. | 6 // License. See LICENSE.TXT for details. |
| 7 // | 7 // |
| 8 //===----------------------------------------------------------------------===// | 8 //===----------------------------------------------------------------------===// |
| 9 /// | 9 /// |
| 10 /// \file | 10 /// \file |
| (...skipping 751 matching lines...) Expand 10 before | Expand all | Expand 10 after Loading... |
| 762 CondARM32::Cond Pred = CondARM32::AL) { | 762 CondARM32::Cond Pred = CondARM32::AL) { |
| 763 Context.insert<InstARM32Uxt>(Dest, Src0, Pred); | 763 Context.insert<InstARM32Uxt>(Dest, Src0, Pred); |
| 764 } | 764 } |
| 765 void _vabs(Variable *Dest, Variable *Src, | 765 void _vabs(Variable *Dest, Variable *Src, |
| 766 CondARM32::Cond Pred = CondARM32::AL) { | 766 CondARM32::Cond Pred = CondARM32::AL) { |
| 767 Context.insert<InstARM32Vabs>(Dest, Src, Pred); | 767 Context.insert<InstARM32Vabs>(Dest, Src, Pred); |
| 768 } | 768 } |
| 769 void _vadd(Variable *Dest, Variable *Src0, Variable *Src1) { | 769 void _vadd(Variable *Dest, Variable *Src0, Variable *Src1) { |
| 770 Context.insert<InstARM32Vadd>(Dest, Src0, Src1); | 770 Context.insert<InstARM32Vadd>(Dest, Src0, Src1); |
| 771 } | 771 } |
| 772 void _vand(Variable *Dest, Variable *Src0, Variable *Src1) { |
| 773 Context.insert<InstARM32Vand>(Dest, Src0, Src1); |
| 774 } |
| 772 void _vcvt(Variable *Dest, Variable *Src, InstARM32Vcvt::VcvtVariant Variant, | 775 void _vcvt(Variable *Dest, Variable *Src, InstARM32Vcvt::VcvtVariant Variant, |
| 773 CondARM32::Cond Pred = CondARM32::AL) { | 776 CondARM32::Cond Pred = CondARM32::AL) { |
| 774 Context.insert<InstARM32Vcvt>(Dest, Src, Variant, Pred); | 777 Context.insert<InstARM32Vcvt>(Dest, Src, Variant, Pred); |
| 775 } | 778 } |
| 776 void _vdiv(Variable *Dest, Variable *Src0, Variable *Src1) { | 779 void _vdiv(Variable *Dest, Variable *Src0, Variable *Src1) { |
| 777 Context.insert<InstARM32Vdiv>(Dest, Src0, Src1); | 780 Context.insert<InstARM32Vdiv>(Dest, Src0, Src1); |
| 778 } | 781 } |
| 779 void _vcmp(Variable *Src0, Variable *Src1, | 782 void _vcmp(Variable *Src0, Variable *Src1, |
| 780 CondARM32::Cond Pred = CondARM32::AL) { | 783 CondARM32::Cond Pred = CondARM32::AL) { |
| 781 Context.insert<InstARM32Vcmp>(Src0, Src1, Pred); | 784 Context.insert<InstARM32Vcmp>(Src0, Src1, Pred); |
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| 1202 private: | 1205 private: |
| 1203 ~TargetHeaderARM32() = default; | 1206 ~TargetHeaderARM32() = default; |
| 1204 | 1207 |
| 1205 TargetARM32Features CPUFeatures; | 1208 TargetARM32Features CPUFeatures; |
| 1206 }; | 1209 }; |
| 1207 | 1210 |
| 1208 } // end of namespace ARM32 | 1211 } // end of namespace ARM32 |
| 1209 } // end of namespace Ice | 1212 } // end of namespace Ice |
| 1210 | 1213 |
| 1211 #endif // SUBZERO_SRC_ICETARGETLOWERINGARM32_H | 1214 #endif // SUBZERO_SRC_ICETARGETLOWERINGARM32_H |
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