Clean up emitInst() in the integrated ARM assembler.

src/IceAssemblerARM32.cpp

 //===- subzero/src/IceAssemblerARM32.cpp - Assembler for ARM32 --*- C++ -*-===//
 //
 // Copyright (c) 2013, the Dart project authors.  Please see the AUTHORS file
 // for details. All rights reserved. Use of this source code is governed by a
 // BSD-style license that can be found in the LICENSE file.
 //
 // Modified by the Subzero authors.
 //
 //===----------------------------------------------------------------------===//
 //
@@ skipping 643 matching lines @@
                                 EmitChecks RuleChecks, const char *InstName) {
   switch (RuleChecks) {
   case NoChecks:
     break;
   case RdIsPcAndSetFlags:
     verifyRegNotPcWhenSetFlags(Rd, SetFlags, InstName);
     break;
   }
   assert(Rd < RegARM32::getNumGPRegs());
   assert(CondARM32::isDefined(Cond));
-  AssemblerBuffer::EnsureCapacity ensured(&Buffer);
   const IValueT Encoding = (encodeCondition(Cond) << kConditionShift) |
                            (InstType << kTypeShift) | (Opcode << kOpcodeShift) |
                            (encodeBool(SetFlags) << kSShift) |
                            (Rn << kRnShift) | (Rd << kRdShift) | Imm12;
   emitInst(Encoding);
 }
 
 void AssemblerARM32::emitType01(CondARM32::Cond Cond, IValueT Opcode,
                                 const Operand *OpRd, const Operand *OpRn,
                                 const Operand *OpSrc1, bool SetFlags,
@@ skipping 65 matching lines @@
   }
   }
 }
 
 void AssemblerARM32::emitType05(CondARM32::Cond Cond, IOffsetT Offset,
                                 bool Link) {
   // cccc101liiiiiiiiiiiiiiiiiiiiiiii where cccc=Cond, l=Link, and
   // iiiiiiiiiiiiiiiiiiiiiiii=
   // EncodedBranchOffset(cccc101l000000000000000000000000, Offset);
   assert(CondARM32::isDefined(Cond));
-  AssemblerBuffer::EnsureCapacity ensured(&Buffer);
   IValueT Encoding = static_cast<int32_t>(Cond) << kConditionShift |
                      5 << kTypeShift | (Link ? 1 : 0) << kLinkShift;
   Encoding = encodeBranchOffset(Offset, Encoding);
   emitInst(Encoding);
 }
 
 void AssemblerARM32::emitBranch(Label *L, CondARM32::Cond Cond, bool Link) {
   // TODO(kschimpf): Handle far jumps.
   if (L->isBound()) {
     const int32_t Dest = L->getPosition() - Buffer.size();
@@ skipping 26 matching lines @@
   constexpr IValueT Rd = RegARM32::Encoded_Reg_r0;
   IValueT Rn = encodeGPRegister(OpRn, "Rn", InstName);
   emitType01(Cond, Opcode, Rd, Rn, OpSrc1, SetFlags, NoChecks, InstName);
 }
 
 void AssemblerARM32::emitMemOp(CondARM32::Cond Cond, IValueT InstType,
                                bool IsLoad, bool IsByte, IValueT Rt,
                                IValueT Address) {
   assert(Rt < RegARM32::getNumGPRegs());
   assert(CondARM32::isDefined(Cond));
-  AssemblerBuffer::EnsureCapacity ensured(&Buffer);
   const IValueT Encoding = (encodeCondition(Cond) << kConditionShift) |
                            (InstType << kTypeShift) | (IsLoad ? L : 0) |
                            (IsByte ? B : 0) | (Rt << kRdShift) | Address;
   emitInst(Encoding);
 }
 
 void AssemblerARM32::emitMemOp(CondARM32::Cond Cond, bool IsLoad, bool IsByte,
                                IValueT Rt, const Operand *OpAddress,
                                const TargetInfo &TInfo, const char *InstName) {
   IValueT Address;
@@ skipping 69 matching lines @@
     // iiiijjjj=Imm8, pu0w<<21 is a BlockAddr, x000000000000yyyy0000=Opcode,
     // and pu0w0nnnn0000iiii0000jjjj=Address.
     assert(Rt < RegARM32::getNumGPRegs());
     assert(CondARM32::isDefined(Cond));
     verifyPOrNotW(Address, InstName);
     verifyRegNotPc(Rt, "Rt", InstName);
     if (isBitSet(W, Address))
       verifyRegsNotEq(getGPRReg(kRnShift, Address), "Rn", Rt, "Rt", InstName);
     const IValueT Encoding = (encodeCondition(Cond) << kConditionShift) |
                              Opcode | (Rt << kRdShift) | Address;
-    AssemblerBuffer::EnsureCapacity ensured(&Buffer);
     emitInst(Encoding);
     return;
   }
   case EncodedAsShiftRotateImm5: {
     // XXXH (register)
     //   xxxh<c> <Rt>, [<Rn>, +/-<Rm>]{!}
     //   xxxh<c> <Rt>, [<Rn>], +/-<Rm>
     //
     // cccc000pu0wxnnnntttt00001011mmmm where cccc=Cond, tttt=Rt, nnnn=Rn,
     // mmmm=Rm, pu0w<<21 is a BlockAddr, x000000000000yyyy0000=Opcode, and
     // pu0w0nnnn000000000000mmmm=Address.
     assert(Rt < RegARM32::getNumGPRegs());
     assert(CondARM32::isDefined(Cond));
     verifyPOrNotW(Address, InstName);
     verifyRegNotPc(Rt, "Rt", InstName);
     verifyAddrRegNotPc(kRmShift, Address, "Rm", InstName);
     const RegARM32::GPRRegister Rn = getGPRReg(kRnShift, Address);
     if (isBitSet(W, Address)) {
       verifyRegNotPc(Rn, "Rn", InstName);
       verifyRegsNotEq(Rn, "Rn", Rt, "Rt", InstName);
     }
     if (mask(Address, kShiftImmShift, 5) != 0)
       // For encoding 3, no shift is allowed.
       llvm::report_fatal_error(std::string(InstName) +
                                ": Shift constant not allowed");
     const IValueT Encoding = (encodeCondition(Cond) << kConditionShift) |
                              Opcode | (Rt << kRdShift) | Address;
-    AssemblerBuffer::EnsureCapacity ensured(&Buffer);
     emitInst(Encoding);
     return;
   }
   }
 }
 
 void AssemblerARM32::emitDivOp(CondARM32::Cond Cond, IValueT Opcode, IValueT Rd,
                                IValueT Rn, IValueT Rm) {
   assert(Rd < RegARM32::getNumGPRegs());
   assert(Rn < RegARM32::getNumGPRegs());
   assert(Rm < RegARM32::getNumGPRegs());
   assert(CondARM32::isDefined(Cond));
-  AssemblerBuffer::EnsureCapacity ensured(&Buffer);
   const IValueT Encoding = Opcode | (encodeCondition(Cond) << kConditionShift) |
                            (Rn << kDivRnShift) | (Rd << kDivRdShift) | B26 |
                            B25 | B24 | B20 | B15 | B14 | B13 | B12 | B4 |
                            (Rm << kDivRmShift);
   emitInst(Encoding);
 }
 
 void AssemblerARM32::emitMulOp(CondARM32::Cond Cond, IValueT Opcode, IValueT Rd,
                                IValueT Rn, IValueT Rm, IValueT Rs,
                                bool SetFlags) {
   assert(Rd < RegARM32::getNumGPRegs());
   assert(Rn < RegARM32::getNumGPRegs());
   assert(Rm < RegARM32::getNumGPRegs());
   assert(Rs < RegARM32::getNumGPRegs());
   assert(CondARM32::isDefined(Cond));
-  AssemblerBuffer::EnsureCapacity ensured(&Buffer);
   IValueT Encoding = Opcode | (encodeCondition(Cond) << kConditionShift) |
                      (encodeBool(SetFlags) << kSShift) | (Rn << kRnShift) |
                      (Rd << kRdShift) | (Rs << kRsShift) | B7 | B4 |
                      (Rm << kRmShift);
   emitInst(Encoding);
 }
 
 void AssemblerARM32::emitMultiMemOp(CondARM32::Cond Cond,
                                     BlockAddressMode AddressMode, bool IsLoad,
                                     IValueT BaseReg, IValueT Registers) {
   assert(CondARM32::isDefined(Cond));
   assert(BaseReg < RegARM32::getNumGPRegs());
   assert(Registers < (1 << RegARM32::getNumGPRegs()));
-  AssemblerBuffer::EnsureCapacity ensured(&Buffer);
   IValueT Encoding = (encodeCondition(Cond) << kConditionShift) | B27 |
                      AddressMode | (IsLoad ? L : 0) | (BaseReg << kRnShift) |
                      Registers;
   emitInst(Encoding);
 }
 
 void AssemblerARM32::emitSignExtend(CondARM32::Cond Cond, IValueT Opcode,
                                     const Operand *OpRd, const Operand *OpSrc0,
                                     const char *InstName) {
   IValueT Rd = encodeGPRegister(OpRd, "Rd", InstName);
@@ skipping 26 matching lines @@
     Opcode |= B20;
     break;
   }
   }
 
   assert(CondARM32::isDefined(Cond));
   IValueT Rot = encodeRotation(Rotation);
   if (!Utils::IsUint(2, Rot))
     llvm::report_fatal_error(std::string(InstName) +
                              ": Illegal rotation value");
-  AssemblerBuffer::EnsureCapacity ensured(&Buffer);
   IValueT Encoding = (encodeCondition(Cond) << kConditionShift) | Opcode |
                      (Rn << kRnShift) | (Rd << kRdShift) |
                      (Rot << kRotationShift) | B6 | B5 | B4 | (Rm << kRmShift);
   emitInst(Encoding);
 }
 
 void AssemblerARM32::emitVFPddd(CondARM32::Cond Cond, IValueT Opcode,
                                 IValueT Dd, IValueT Dn, IValueT Dm) {
   assert(Dd < RegARM32::getNumDRegs());
   assert(Dn < RegARM32::getNumDRegs());
   assert(Dm < RegARM32::getNumDRegs());
   assert(CondARM32::isDefined(Cond));
-  AssemblerBuffer::EnsureCapacity ensured(&Buffer);
   constexpr IValueT VFPOpcode = B27 | B26 | B25 | B11 | B9 | B8;
   const IValueT Encoding =
       Opcode | VFPOpcode | (encodeCondition(Cond) << kConditionShift) |
       (getYInRegYXXXX(Dd) << 22) | (getXXXXInRegYXXXX(Dn) << 16) |
       (getXXXXInRegYXXXX(Dd) << 12) | (getYInRegYXXXX(Dn) << 7) |
       (getYInRegYXXXX(Dm) << 5) | getXXXXInRegYXXXX(Dm);
   emitInst(Encoding);
 }
 
 void AssemblerARM32::emitVFPsss(CondARM32::Cond Cond, IValueT Opcode,
                                 IValueT Sd, IValueT Sn, IValueT Sm) {
   assert(Sd < RegARM32::getNumSRegs());
   assert(Sn < RegARM32::getNumSRegs());
   assert(Sm < RegARM32::getNumSRegs());
   assert(CondARM32::isDefined(Cond));
-  AssemblerBuffer::EnsureCapacity ensured(&Buffer);
   constexpr IValueT VFPOpcode = B27 | B26 | B25 | B11 | B9;
   const IValueT Encoding =
       Opcode | VFPOpcode | (encodeCondition(Cond) << kConditionShift) |
       (getYInRegXXXXY(Sd) << 22) | (getXXXXInRegXXXXY(Sn) << 16) |
       (getXXXXInRegXXXXY(Sd) << 12) | (getYInRegXXXXY(Sn) << 7) |
       (getYInRegXXXXY(Sm) << 5) | getXXXXInRegXXXXY(Sm);
   emitInst(Encoding);
 }
 
 void AssemblerARM32::adc(const Operand *OpRd, const Operand *OpRn,
@@ skipping 62 matching lines @@
 
 void AssemblerARM32::b(Label *L, CondARM32::Cond Cond) {
   emitBranch(L, Cond, false);
 }
 
 void AssemblerARM32::bkpt(uint16_t Imm16) {
   // BKPT - ARM section A*.8.24 - encoding A1:
   //   bkpt #<Imm16>
   //
   // cccc00010010iiiiiiiiiiii0111iiii where cccc=AL and iiiiiiiiiiiiiiii=Imm16
-  AssemblerBuffer::EnsureCapacity ensured(&Buffer);
   const IValueT Encoding = (CondARM32::AL << kConditionShift) | B24 | B21 |
                            ((Imm16 >> 4) << 8) | B6 | B5 | B4 | (Imm16 & 0xf);
   emitInst(Encoding);
 }
 
 void AssemblerARM32::bic(const Operand *OpRd, const Operand *OpRn,
                          const Operand *OpSrc1, bool SetFlags,
                          CondARM32::Cond Cond) {
   // BIC (register) - ARM section A8.8.22, encoding A1:
   //   bic{s}<c> <Rd>, <Rn>, <Rm>{, <shift>}
@@ skipping 27 matching lines @@
 
 void AssemblerARM32::blx(const Operand *Target) {
   // BLX (register) - ARM section A8.8.26, encoding A1:
   //   blx<c> <Rm>
   //
   // cccc000100101111111111110011mmmm where cccc=Cond (not currently allowed)
   // and mmmm=Rm.
   constexpr const char *BlxName = "Blx";
   IValueT Rm = encodeGPRegister(Target, "Rm", BlxName);
   verifyRegNotPc(Rm, "Rm", BlxName);
-  AssemblerBuffer::EnsureCapacity ensured(&Buffer);
   constexpr CondARM32::Cond Cond = CondARM32::AL;
   int32_t Encoding = (encodeCondition(Cond) << kConditionShift) | B24 | B21 |
                      (0xfff << 8) | B5 | B4 | (Rm << kRmShift);
   emitInst(Encoding);
 }
 
 void AssemblerARM32::bx(RegARM32::GPRRegister Rm, CondARM32::Cond Cond) {
   // BX - ARM section A8.8.27, encoding A1:
   //   bx<c> <Rm>
   //
   // cccc000100101111111111110001mmmm where mmmm=rm and cccc=Cond.
   assert(CondARM32::isDefined(Cond));
-  AssemblerBuffer::EnsureCapacity ensured(&Buffer);
   const IValueT Encoding = (encodeCondition(Cond) << kConditionShift) | B24 |
                            B21 | (0xfff << 8) | B4 |
                            (encodeGPRRegister(Rm) << kRmShift);
   emitInst(Encoding);
 }
 
 void AssemblerARM32::clz(const Operand *OpRd, const Operand *OpSrc,
                          CondARM32::Cond Cond) {
   // CLZ - ARM section A8.8.33, encoding A1:
   //   clz<c> <Rd> <Rm>
   //
   // cccc000101101111dddd11110001mmmm where cccc=Cond, dddd=Rd, and mmmm=Rm.
   constexpr const char *ClzName = "clz";
   constexpr const char *RdName = "Rd";
   constexpr const char *RmName = "Rm";
   IValueT Rd = encodeGPRegister(OpRd, RdName, ClzName);
   assert(Rd < RegARM32::getNumGPRegs());
   verifyRegNotPc(Rd, RdName, ClzName);
   IValueT Rm = encodeGPRegister(OpSrc, RmName, ClzName);
   assert(Rm < RegARM32::getNumGPRegs());
   verifyRegNotPc(Rm, RmName, ClzName);
   assert(CondARM32::isDefined(Cond));
-  AssemblerBuffer::EnsureCapacity ensured(&Buffer);
   constexpr IValueT PredefinedBits =
       B24 | B22 | B21 | (0xF << 16) | (0xf << 8) | B4;
   const IValueT Encoding = PredefinedBits | (Cond << kConditionShift) |
                            (Rd << kRdShift) | (Rm << kRmShift);
   emitInst(Encoding);
 }
 
 void AssemblerARM32::cmn(const Operand *OpRn, const Operand *OpSrc1,
                          CondARM32::Cond Cond) {
   // CMN (immediate) - ARM section A8.8.34, encoding A1:
@@ skipping 29 matching lines @@
   constexpr IValueT CmpOpcode = B3 | B1; // ie. 1010
   emitCompareOp(Cond, CmpOpcode, OpRn, OpSrc1, CmpName);
 }
 
 void AssemblerARM32::dmb(IValueT Option) {
   // DMB - ARM section A8.8.43, encoding A1:
   //   dmb <option>
   //
   // 1111010101111111111100000101xxxx where xxxx=Option.
   assert(Utils::IsUint(4, Option) && "Bad dmb option");
-  AssemblerBuffer::EnsureCapacity ensured(&Buffer);
   const IValueT Encoding =
       (encodeCondition(CondARM32::kNone) << kConditionShift) | B26 | B24 | B22 |
       B21 | B20 | B19 | B18 | B17 | B16 | B15 | B14 | B13 | B12 | B6 | B4 |
       Option;
   emitInst(Encoding);
 }
 
 void AssemblerARM32::eor(const Operand *OpRd, const Operand *OpRn,
                          const Operand *OpSrc1, bool SetFlags,
                          CondARM32::Cond Cond) {
@@ skipping 111 matching lines @@
   }
   IValueT AddressRn;
   if (encodeAddress(OpAddress, AddressRn, TInfo, OpEncodingMemEx) !=
       EncodedAsImmRegOffset)
     llvm::report_fatal_error(std::string(InstName) +
                              ": Can't extract Rn from address");
   assert(Utils::IsAbsoluteUint(3, MemExOpcode));
   assert(Rd < RegARM32::getNumGPRegs());
   assert(Rt < RegARM32::getNumGPRegs());
   assert(CondARM32::isDefined(Cond));
-  AssemblerBuffer::EnsureCapacity ensured(&Buffer);
   IValueT Encoding = (Cond << kConditionShift) | B24 | B23 | B11 | B10 | B9 |
                      B8 | B7 | B4 | (MemExOpcode << kMemExOpcodeShift) |
                      AddressRn | (Rd << kRdShift) | (Rt << kRmShift);
   emitInst(Encoding);
   return;
 }
 
 void AssemblerARM32::ldrex(const Operand *OpRt, const Operand *OpAddress,
                            CondARM32::Cond Cond, const TargetInfo &TInfo) {
   // LDREXB - ARM section A8.8.76, encoding A1:
@@ skipping 119 matching lines @@
     emitFixup(createMoveFixup(IsMovW, Src));
     // Use 0 for the lower 16 bits of the relocatable, and add a fixup to
     // install the correct bits.
     Imm16 = 0;
   } else if (encodeOperand(OpSrc, Imm16, WantGPRegs) != EncodedAsConstI32) {
     llvm::report_fatal_error(std::string(MovName) + ": Not i32 constant");
   }
   assert(CondARM32::isDefined(Cond));
   if (!Utils::IsAbsoluteUint(16, Imm16))
     llvm::report_fatal_error(std::string(MovName) + ": Constant not i16");
-  AssemblerBuffer::EnsureCapacity ensured(&Buffer);
   const IValueT Encoding = encodeCondition(Cond) << kConditionShift | Opcode |
                            ((Imm16 >> 12) << 16) | Rd << kRdShift |
                            (Imm16 & 0xfff);
   emitInst(Encoding);
 }
 
 void AssemblerARM32::movw(const Operand *OpRd, const Operand *OpSrc,
                           CondARM32::Cond Cond) {
   // MOV (immediate) - ARM section A8.8.102, encoding A2:
   //  movw<c> <Rd>, #<imm16>
@@ skipping 37 matching lines @@
   constexpr bool SetFlags = false;
   emitType01(Cond, MvnOpcode, Rd, Rn, OpSrc, SetFlags, RdIsPcAndSetFlags,
              MvnName);
 }
 
 void AssemblerARM32::nop() {
   // NOP - Section A8.8.119, encoding A1:
   //  nop<c>
   //
   // cccc0011001000001111000000000000 where cccc=Cond.
-  AssemblerBuffer::EnsureCapacity ensured(&Buffer);
   constexpr CondARM32::Cond Cond = CondARM32::AL;
   const IValueT Encoding = (encodeCondition(Cond) << kConditionShift) | B25 |
                            B24 | B21 | B15 | B14 | B13 | B12;
   emitInst(Encoding);
 }
 
 void AssemblerARM32::sbc(const Operand *OpRd, const Operand *OpRn,
                          const Operand *OpSrc1, bool SetFlags,
                          CondARM32::Cond Cond) {
   // SBC (register) - ARM section 18.8.162, encoding A1:
@@ skipping 257 matching lines @@
   // Assembler registers rd, rn, rm are encoded as rn, rm, rs.
   constexpr IValueT MulOpcode = 0;
   emitMulOp(Cond, MulOpcode, RegARM32::Encoded_Reg_r0, Rd, Rn, Rm, SetFlags);
 }
 
 void AssemblerARM32::emitRdRm(CondARM32::Cond Cond, IValueT Opcode,
                               const Operand *OpRd, const Operand *OpRm,
                               const char *InstName) {
   IValueT Rd = encodeGPRegister(OpRd, "Rd", InstName);
   IValueT Rm = encodeGPRegister(OpRm, "Rm", InstName);
-  AssemblerBuffer::EnsureCapacity ensured(&Buffer);
   IValueT Encoding =
       (Cond << kConditionShift) | Opcode | (Rd << kRdShift) | (Rm << kRmShift);
   emitInst(Encoding);
 }
 
 void AssemblerARM32::rbit(const Operand *OpRd, const Operand *OpRm,
                           CondARM32::Cond Cond) {
   // RBIT - ARM section A8.8.144, encoding A1:
   //   rbit<c> <Rd>, <Rm>
   //
@@ skipping 247 matching lines @@
   constexpr IValueT Sn = 0;
   constexpr IValueT Sm = 0;
   emitVFPsss(Cond, VcmpszOpcode, Sd, Sn, Sm);
 }
 
 void AssemblerARM32::emitVFPsd(CondARM32::Cond Cond, IValueT Opcode, IValueT Sd,
                                IValueT Dm) {
   assert(Sd < RegARM32::getNumSRegs());
   assert(Dm < RegARM32::getNumDRegs());
   assert(CondARM32::isDefined(Cond));
-  AssemblerBuffer::EnsureCapacity ensured(&Buffer);
   constexpr IValueT VFPOpcode = B27 | B26 | B25 | B11 | B9;
   const IValueT Encoding =
       Opcode | VFPOpcode | (encodeCondition(Cond) << kConditionShift) |
       (getYInRegXXXXY(Sd) << 22) | (getXXXXInRegXXXXY(Sd) << 12) |
       (getYInRegYXXXX(Dm) << 5) | getXXXXInRegYXXXX(Dm);
   emitInst(Encoding);
 }
 
 void AssemblerARM32::vcvtdi(const Operand *OpDd, const Operand *OpSm,
                             CondARM32::Cond Cond) {
@@ skipping 120 matching lines @@
   constexpr IValueT VcvtsiOpcode = B23 | B21 | B20 | B19 | B18 | B7 | B6;
   constexpr IValueT S0 = 0;
   emitVFPsss(Cond, VcvtsiOpcode, Sd, S0, Sm);
 }
 
 void AssemblerARM32::emitVFPds(CondARM32::Cond Cond, IValueT Opcode, IValueT Dd,
                                IValueT Sm) {
   assert(Dd < RegARM32::getNumDRegs());
   assert(Sm < RegARM32::getNumSRegs());
   assert(CondARM32::isDefined(Cond));
-  AssemblerBuffer::EnsureCapacity ensured(&Buffer);
   constexpr IValueT VFPOpcode = B27 | B26 | B25 | B11 | B9;
   const IValueT Encoding =
       Opcode | VFPOpcode | (encodeCondition(Cond) << kConditionShift) |
       (getYInRegYXXXX(Dd) << 22) | (getXXXXInRegYXXXX(Dd) << 12) |
       (getYInRegXXXXY(Sm) << 5) | getXXXXInRegXXXXY(Sm);
   emitInst(Encoding);
 }
 
 void AssemblerARM32::vcvtds(const Operand *OpDd, const Operand *OpSm,
                             CondARM32::Cond Cond) {
@@ skipping 37 matching lines @@
 void AssemblerARM32::veord(const Operand *OpDd, const Operand *OpDn,
                            const Operand *OpDm) {
   // VEOR - ARM secdtion A8.8.315, encoding A1:
   //   veor<c> <Dd>, <Dn>, <Dm>
   //
   // 111100110D00nnnndddd0001N0M1mmmm where Ddddd=Dd, Nnnnn=Dn, and Mmmmm=Dm.
   constexpr const char *Veord = "veord";
   IValueT Dd = encodeDRegister(OpDd, "Dd", Veord);
   IValueT Dn = encodeDRegister(OpDn, "Dn", Veord);
   IValueT Dm = encodeDRegister(OpDm, "Dm", Veord);
-  AssemblerBuffer::EnsureCapacity ensured(&Buffer);
   const IValueT Encoding =
       B25 | B24 | B8 | B4 |
       (encodeCondition(CondARM32::Cond::kNone) << kConditionShift) |
       (getYInRegYXXXX(Dd) << 22) | (getXXXXInRegYXXXX(Dn) << 16) |
       (getXXXXInRegYXXXX(Dd) << 12) | (getYInRegYXXXX(Dn) << 7) |
       (getYInRegYXXXX(Dm) << 5) | getXXXXInRegYXXXX(Dm);
   emitInst(Encoding);
 }
 
 void AssemblerARM32::vldrd(const Operand *OpDd, const Operand *OpAddress,
                            CondARM32::Cond Cond, const TargetInfo &TInfo) {
   // VLDR - ARM section A8.8.333, encoding A1.
   //   vldr<c> <Dd>, [<Rn>{, #+/-<imm>}]
   //
   // cccc1101UD01nnnndddd1011iiiiiiii where cccc=Cond, nnnn=Rn, Ddddd=Rd,
   // iiiiiiii=abs(Imm >> 2), and U=1 if Opcode>=0.
   constexpr const char *Vldrd = "vldrd";
   IValueT Dd = encodeDRegister(OpDd, "Dd", Vldrd);
   assert(CondARM32::isDefined(Cond));
   IValueT Address;
   EncodedOperand AddressEncoding =
       encodeAddress(OpAddress, Address, TInfo, ImmRegOffsetDiv4);
   (void)AddressEncoding;
   assert(AddressEncoding == EncodedAsImmRegOffset);
-  AssemblerBuffer::EnsureCapacity ensured(&Buffer);
   IValueT Encoding = B27 | B26 | B24 | B20 | B11 | B9 | B8 |
                      (encodeCondition(Cond) << kConditionShift) |
                      (getYInRegYXXXX(Dd) << 22) |
                      (getXXXXInRegYXXXX(Dd) << 12) | Address;
   emitInst(Encoding);
 }
 
 void AssemblerARM32::vldrs(const Operand *OpSd, const Operand *OpAddress,
                            CondARM32::Cond Cond, const TargetInfo &TInfo) {
   // VDLR - ARM section A8.8.333, encoding A2.
   //   vldr<c> <Sd>, [<Rn>{, #+/-<imm>]]
   //
   // cccc1101UD01nnnndddd1010iiiiiiii where cccc=Cond, nnnn=Rn, ddddD=Sd,
   // iiiiiiii=abs(Opcode), and U=1 if Opcode >= 0;
   constexpr const char *Vldrs = "vldrs";
   IValueT Sd = encodeSRegister(OpSd, "Sd", Vldrs);
   assert(CondARM32::isDefined(Cond));
   IValueT Address;
   EncodedOperand AddressEncoding =
       encodeAddress(OpAddress, Address, TInfo, ImmRegOffsetDiv4);
   (void)AddressEncoding;
   assert(AddressEncoding == EncodedAsImmRegOffset);
-  AssemblerBuffer::EnsureCapacity ensured(&Buffer);
   IValueT Encoding = B27 | B26 | B24 | B20 | B11 | B9 |
                      (encodeCondition(Cond) << kConditionShift) |
                      (getYInRegXXXXY(Sd) << 22) |
                      (getXXXXInRegXXXXY(Sd) << 12) | Address;
   emitInst(Encoding);
 }
 
 void AssemblerARM32::vmovsr(const Operand *OpSn, const Operand *OpRt,
                             CondARM32::Cond Cond) {
   // VMOV (between ARM core register and single-precision register)
   //   ARM section A8.8.343, encoding A1.
   //
   //   vmov<c> <Sn>, <Rt>
   //
   // cccc1110000onnnntttt1010N0010000 where cccc=Cond, nnnnN = Sn, and tttt=Rt.
   constexpr const char *Vmovsr = "vmovsr";
   IValueT Sn = encodeSRegister(OpSn, "Sn", Vmovsr);
   IValueT Rt = encodeGPRegister(OpRt, "Rt", Vmovsr);
   assert(Sn < RegARM32::getNumSRegs());
   assert(Rt < RegARM32::getNumGPRegs());
   assert(CondARM32::isDefined(Cond));
-  AssemblerBuffer::EnsureCapacity ensured(&Buffer);
   IValueT Encoding = (encodeCondition(Cond) << kConditionShift) | B27 | B26 |
                      B25 | B11 | B9 | B4 | (getXXXXInRegXXXXY(Sn) << 16) |
                      (Rt << kRdShift) | (getYInRegXXXXY(Sn) << 7);
   emitInst(Encoding);
 }
 
 void AssemblerARM32::vmrsAPSR_nzcv(CondARM32::Cond Cond) {
   // MVRS - ARM section A*.8.348, encoding A1:
   //   vmrs<c> APSR_nzcv, FPSCR
   //
   // cccc111011110001tttt101000010000 where tttt=0x15 (i.e. when Rt=pc, use
   // APSR_nzcv instead).
   assert(CondARM32::isDefined(Cond));
   IValueT Encoding = B27 | B26 | B25 | B23 | B22 | B21 | B20 | B16 | B15 | B14 |
                      B13 | B12 | B11 | B9 | B4 |
                      (encodeCondition(Cond) << kConditionShift);
-  AssemblerBuffer::EnsureCapacity ensured(&Buffer);
   emitInst(Encoding);
 }
 
 void AssemblerARM32::vmuls(const Operand *OpSd, const Operand *OpSn,
                            const Operand *OpSm, CondARM32::Cond Cond) {
   // VMUL (floating-point) - ARM section A8.8.351, encoding A2:
   //   vmul<c>.f32 <Sd>, <Sn>, <Sm>
   //
   // cccc11100D10nnnndddd101sN0M0mmmm where cccc=Cond, s=0, ddddD=Rd, nnnnN=Rn,
   // and mmmmM=Rm.
@@ skipping 28 matching lines @@
   // cccc1101UD00nnnndddd1011iiiiiiii where cccc=Cond, nnnn=Rn, Ddddd=Rd,
   // iiiiiiii=abs(Imm >> 2), and U=1 if Imm>=0.
   constexpr const char *Vstrd = "vstrd";
   IValueT Dd = encodeDRegister(OpDd, "Dd", Vstrd);
   assert(CondARM32::isDefined(Cond));
   IValueT Address;
   IValueT AddressEncoding =
       encodeAddress(OpAddress, Address, TInfo, ImmRegOffsetDiv4);
   (void)AddressEncoding;
   assert(AddressEncoding == EncodedAsImmRegOffset);
-  AssemblerBuffer::EnsureCapacity ensured(&Buffer);
   IValueT Encoding = B27 | B26 | B24 | B11 | B9 | B8 |
                      (encodeCondition(Cond) << kConditionShift) |
                      (getYInRegYXXXX(Dd) << 22) |
                      (getXXXXInRegYXXXX(Dd) << 12) | Address;
   emitInst(Encoding);
 }
 
 void AssemblerARM32::vstrs(const Operand *OpSd, const Operand *OpAddress,
                            CondARM32::Cond Cond, const TargetInfo &TInfo) {
   // VSTR - ARM section A8.8.413, encoding A2:
   //   vstr<c> <Sd>, [<Rn>{, #+/-<imm>]]
   //
   // cccc1101UD01nnnndddd1010iiiiiiii where cccc=Cond, nnnn=Rn, ddddD=Sd,
   // iiiiiiii=abs(Opcode), and U=1 if Opcode >= 0;
   constexpr const char *Vstrs = "vstrs";
   IValueT Sd = encodeSRegister(OpSd, "Sd", Vstrs);
   assert(CondARM32::isDefined(Cond));
   IValueT Address;
   IValueT AddressEncoding =
       encodeAddress(OpAddress, Address, TInfo, ImmRegOffsetDiv4);
   (void)AddressEncoding;
   assert(AddressEncoding == EncodedAsImmRegOffset);
-  AssemblerBuffer::EnsureCapacity ensured(&Buffer);
   IValueT Encoding =
       B27 | B26 | B24 | B11 | B9 | (encodeCondition(Cond) << kConditionShift) |
       (getYInRegXXXXY(Sd) << 22) | (getXXXXInRegXXXXY(Sd) << 12) | Address;
   emitInst(Encoding);
 }
 
 void AssemblerARM32::vsubs(const Operand *OpSd, const Operand *OpSn,
                            const Operand *OpSm, CondARM32::Cond Cond) {
   // VSUB (floating-point) - ARM section A8.8.415, encoding A2:
   //   vsub<c>.f32 <Sd>, <Sn>, <Sm>
@@ skipping 27 matching lines @@
                                   const Variable *OpBaseReg,
                                   SizeT NumConsecRegs) {
   const IValueT BaseReg = getEncodedSRegNum(OpBaseReg);
   const IValueT DLastBit = mask(BaseReg, 0, 1); // Last bit of base register.
   const IValueT Rd = mask(BaseReg, 1, 4);       // Top 4 bits of base register.
   assert(0 < NumConsecRegs);
   (void)VpushVpopMaxConsecRegs;
   assert(NumConsecRegs <= VpushVpopMaxConsecRegs);
   assert((BaseReg + NumConsecRegs) <= RegARM32::getNumSRegs());
   assert(CondARM32::isDefined(Cond));
-  AssemblerBuffer::EnsureCapacity ensured(&Buffer);
   const IValueT Encoding = Opcode | (Cond << kConditionShift) | DLastBit |
                            (Rd << kRdShift) | NumConsecRegs;
   emitInst(Encoding);
 }
 
 void AssemblerARM32::vpop(const Variable *OpBaseReg, SizeT NumConsecRegs,
                           CondARM32::Cond Cond) {
   // Note: Current implementation assumes that OpBaseReg is defined using S
   // registers. It doesn't implement the D register form.
   //
@@ skipping 17 matching lines @@
   //
   // cccc11010D101101dddd1010iiiiiiii where cccc=Cond, ddddD=BaseReg, and
   // iiiiiiii=NumConsecRegs.
   constexpr IValueT VpushOpcode =
       B27 | B26 | B24 | B21 | B19 | B18 | B16 | B11 | B9;
   emitVStackOp(Cond, VpushOpcode, OpBaseReg, NumConsecRegs);
 }
 
 } // end of namespace ARM32
 } // end of namespace Ice