Add the VMRS instruction to the integrated ARM assembler.

tests_lit/assembler/arm32/vmrs.ll

-; Show that we know how to translate veor. Does this by noting that
-; loading a double 0.0 introduces a veor.
+; Test the "vmrs APSR_nzcv, FPSCR" form of the VMRS instruction.
 
 ; REQUIRES: allow_dump
 
 ; Compile using standalone assembler.
 ; RUN: %p2i --filetype=asm -i %s --target=arm32 --args -Om1 \
 ; RUN:   | FileCheck %s --check-prefix=ASM
 
 ; Show bytes in assembled standalone code.
 ; RUN: %p2i --filetype=asm -i %s --target=arm32 --assemble --disassemble \
 ; RUN:   --args -Om1 \
 ; RUN:   | FileCheck %s --check-prefix=DIS
 
 ; Compile using integrated assembler.
 ; RUN: %p2i --filetype=iasm -i %s --target=arm32 --args -Om1 \
 ; RUN:   | FileCheck %s --check-prefix=IASM
 
 ; Show bytes in assembled integrated code.
 ; RUN: %p2i --filetype=iasm -i %s --target=arm32 --assemble --disassemble \
 ; RUN:   --args -Om1 \
 ; RUN:   | FileCheck %s --check-prefix=DIS
 
-define internal double @testVeor() {
-; ASM-LABEL: testVeor:
-; DIS: 00000000 <testVeor>:
+define internal i32 @testVmrsASPR_nzcv() {
+; ASM-LABEL: testVmrsASPR_nzcv:
+; DIS-LABEL: 00000000 <testVmrsASPR_nzcv>:
 
 entry:
-; ASM: .LtestVeor$entry:
+; ASM: .LtestVmrsASPR_nzcv$entry:
 
-  ret double 0.0
+  %test = fcmp olt float 0.0, 0.0
 
-; ASM:  veor.f64        d0, d0, d0
-; DIS:    0:    f3000110
-; IASM-NOT: veor
+; ASM:  vmrs    APSR_nzcv, FPSCR
+; DIS:   18:    eef1fa10
+; IASM-NOT: vmrs
 
+  %result = zext i1 %test to i32
+  ret i32 %result
 }