Add the VMRS instruction to the integrated ARM assembler.

src/DartARM32/assembler_arm.cc

 // Copyright (c) 2013, the Dart project authors.  Please see the AUTHORS file
 // for details. All rights reserved. Use of this source code is governed by a
 // BSD-style license that can be found in the LICENSE file.
 //
 // This is forked from Dart revision df52deea9f25690eb8b66c5995da92b70f7ac1fe
 // Please update the (git) revision if we merge changes from Dart.
 // https://code.google.com/p/dart/wiki/GettingTheSource
 
 #include "vm/globals.h"  // NOLINT
 #if defined(TARGET_ARCH_ARM)
@@ skipping 1153 matching lines @@
 
 // Moved to ARM23::AssemblerARM32::vcmpsz().
 void Assembler::vcmpsz(SRegister sd, Condition cond) {
   EmitVFPsss(cond, B23 | B21 | B20 | B18 | B16 | B6, sd, S0, S0);
 }
 
 // Moved to ARM23::AssemblerARM32::vcmpdz().
 void Assembler::vcmpdz(DRegister dd, Condition cond) {
   EmitVFPddd(cond, B23 | B21 | B20 | B18 | B16 | B6, dd, D0, D0);
 }
-#endif
 
+// APSR_nzcv version moved to ARM32::AssemblerARM32::vmrsAPSR_nzcv()
 void Assembler::vmrs(Register rd, Condition cond) {
   ASSERT(TargetCPUFeatures::vfp_supported());
   ASSERT(cond != kNoCondition);
   int32_t encoding = (static_cast<int32_t>(cond) << kConditionShift) |
                      B27 | B26 | B25 | B23 | B22 | B21 | B20 | B16 |
                      (static_cast<int32_t>(rd)*B12) |
                      B11 | B9 | B4;
   Emit(encoding);
 }
-
+#endif
 
 void Assembler::vmstat(Condition cond) {
   vmrs(APSR, cond);
 }
 
 
 static inline int ShiftOfOperandSize(OperandSize size) {
   switch (size) {
     case kByte:
     case kUnsignedByte:
@@ skipping 2492 matching lines @@
 
 
 const char* Assembler::FpuRegisterName(FpuRegister reg) {
   ASSERT((0 <= reg) && (reg < kNumberOfFpuRegisters));
   return fpu_reg_names[reg];
 }
 
 }  // namespace dart
 
 #endif  // defined TARGET_ARCH_ARM