Subzero. ARM32. Vector lowering. Add.

tests_lit/assembler/arm32/vldr-float4.ll

Index: tests_lit/assembler/arm32/vldr-float4.ll
diff --git a/tests_lit/assembler/arm32/vldr-float4.ll b/tests_lit/assembler/arm32/vldr-float4.ll
new file mode 100644
index 0000000000000000000000000000000000000000..f38497319d7dcb0646eca69b4db097921fafda0f
--- /dev/null
+++ b/tests_lit/assembler/arm32/vldr-float4.ll
@@ -0,0 +1,42 @@
+; Show that we know how to translate vector load instructions.
+
+; NOTE: Restricts S and D registers to ones that will better test S/D

[Jim Stichnoth, 2016/01/25 21:35:32]

Same comment as in the other .ll file.

+; register encodings.
+
+; REQUIRES: allow_dump
+
+; Compile using standalone assembler.
+; RUN: %p2i --filetype=asm -i %s --target=arm32 --args -O2 \
+; RUN:   -reg-use s20,s22,d20,d22,q0,q11 \
+; RUN:   | FileCheck %s --check-prefix=ASM
+
+; Show bytes in assembled standalone code.
+; RUN: %p2i --filetype=asm -i %s --target=arm32 --assemble --disassemble \
+; RUN:   --args -O2 \
+; RUN:   -reg-use s20,s22,d20,d22,q0,q11 \
+; RUN:   | FileCheck %s --check-prefix=DIS
+
+; Compile using integrated assembler.
+; RUN: %p2i --filetype=iasm -i %s --target=arm32 --args -O2 \
+; RUN:   -reg-use s20,s22,d20,d22,q0,q11 \
+; RUN:   | FileCheck %s --check-prefix=IASM
+
+; Show bytes in assembled integrated code.
+; RUN: %p2i --filetype=iasm -i %s --target=arm32 --assemble --disassemble \
+; RUN:   --args -O2 \
+; RUN:   -reg-use s20,s22,d20,d22,q0,q11 \
+; RUN:   | FileCheck %s --check-prefix=DIS
+
+define internal <4 x float> @testDerefFloat4(<4 x float> *%p) {
+; ASM-LABEL: testDerefFloat4:
+; DIS-LABEL: 00000000 <testDerefFloat4>:
+; IASM-LABEL: testDerefFloat4:
+
+entry:
+  %ret = load <4 x float>, <4 x float>* %p, align 4
+; ASM:     vld1.64	q0, [r0]
+; DIS:   0:       f4200acf
+
+  ret <4 x float> %ret
+}
+

[Jim Stichnoth, 2016/01/25 21:35:32]

Remove trailing blank line, to placate git.