Subzero. ARM32. Vector lowering. Add.

src/IceTargetLoweringARM32.cpp

Index: src/IceTargetLoweringARM32.cpp
diff --git a/src/IceTargetLoweringARM32.cpp b/src/IceTargetLoweringARM32.cpp
index 2d998edd7121235b8989c72e711cb84290f18414..9a8087ec2ca46bb6489c7a999064c6792c5bced2 100644
--- a/src/IceTargetLoweringARM32.cpp
+++ b/src/IceTargetLoweringARM32.cpp
@@ -2798,8 +2798,16 @@ void TargetARM32::lowerArithmetic(const InstArithmetic *Instr) {
   }
 
   if (isVectorType(DestTy)) {
-    UnimplementedLoweringError(this, Instr);
-    return;
+    switch(Instr->getOp()) {
+      default:
+        UnimplementedLoweringError(this, Instr);
+        return;
+      // this explicitly whitelists vector instructions we have some reason to
+      // believe works.
+      case InstArithmetic::Fadd:
+      case InstArithmetic::Add:
+        break;

[Jim Stichnoth, 2016/01/25 21:35:31]

Is it generally true that vector lowering will be basically identical to scalar
lowering, except for minor differences like _vadd instead of _add?   And it
applies as well to the more complicated stuff like mla?  If so, that's really
cool and refreshingly unlike x86.

[Eric Holk, 2016/01/25 23:56:58]

So far this seems true. I was pleasantly surprised. It looks like there might be
subtleties for things like element-wise multiply vs multiply by scalar.

+    }
   }
 
   // DestTy is a non-i64 scalar.

[Jim Stichnoth, 2016/01/25 21:35:31]

This comment is no longer true.

[Eric Holk, 2016/01/25 23:56:58]

I'll remove the comment.

@@ -2900,6 +2908,7 @@ void TargetARM32::lowerArithmetic(const InstArithmetic *Instr) {
     return;
   case InstArithmetic::Add: {
     if (const Inst *Src1Producer = Computations.getProducerOf(Src1)) {
+      assert(!isVectorType(DestTy));
       Variable *Src0R = legalizeToReg(Src0);
       Variable *Src1R = legalizeToReg(Src1Producer->getSrc(0));
       Variable *Src2R = legalizeToReg(Src1Producer->getSrc(1));
@@ -2911,6 +2920,7 @@ void TargetARM32::lowerArithmetic(const InstArithmetic *Instr) {
     if (Srcs.hasConstOperand()) {
       if (!Srcs.immediateIsFlexEncodable() &&
           Srcs.negatedImmediateIsFlexEncodable()) {
+        assert(!isVectorType(DestTy));
         Variable *Src0R = Srcs.src0R(this);
         Operand *Src1F = Srcs.negatedSrc1F(this);
         if (!Srcs.swappedOperands()) {
@@ -2923,8 +2933,14 @@ void TargetARM32::lowerArithmetic(const InstArithmetic *Instr) {
       }
     }
     Variable *Src0R = Srcs.src0R(this);
-    Operand *Src1RF = Srcs.src1RF(this);
-    _add(T, Src0R, Src1RF);
+    if (isVectorType(DestTy)) {
+      Variable *Src1R = legalizeToReg(Src1);
+      _vadd(T, Src0R, Src1R);
+    }
+    else {
+      Operand *Src1RF = Srcs.src1RF(this);
+      _add(T, Src0R, Src1RF);
+    }
     _mov(Dest, T);
     return;
   }