Add VMLA (floating point) to the integrated ARM assembler.

src/IceAssemblerARM32.cpp

 //===- subzero/src/IceAssemblerARM32.cpp - Assembler for ARM32 --*- C++ -*-===//
 //
 // Copyright (c) 2013, the Dart project authors.  Please see the AUTHORS file
 // for details. All rights reserved. Use of this source code is governed by a
 // BSD-style license that can be found in the LICENSE file.
 //
 // Modified by the Subzero authors.
 //
 //===----------------------------------------------------------------------===//
 //
@@ skipping 1027 matching lines @@
   assert(CondARM32::isDefined(Cond));
   constexpr IValueT VFPOpcode = B27 | B26 | B25 | B11 | B9 | B8;
   const IValueT Encoding =
       Opcode | VFPOpcode | (encodeCondition(Cond) << kConditionShift) |
       (getYInRegYXXXX(Dd) << 22) | (getXXXXInRegYXXXX(Dn) << 16) |
       (getXXXXInRegYXXXX(Dd) << 12) | (getYInRegYXXXX(Dn) << 7) |
       (getYInRegYXXXX(Dm) << 5) | getXXXXInRegYXXXX(Dm);
   emitInst(Encoding);
 }
 
+void AssemblerARM32::emitVFPddd(CondARM32::Cond Cond, IValueT Opcode,
+                                const Operand *OpDd, const Operand *OpDn,
+                                const Operand *OpDm, const char *InstName) {
+  IValueT Dd = encodeDRegister(OpDd, "Dd", InstName);
+  IValueT Dn = encodeDRegister(OpDn, "Dn", InstName);
+  IValueT Dm = encodeDRegister(OpDm, "Dm", InstName);
+  emitVFPddd(Cond, Opcode, Dd, Dn, Dm);
+}
+
 void AssemblerARM32::emitVFPsss(CondARM32::Cond Cond, IValueT Opcode,
                                 IValueT Sd, IValueT Sn, IValueT Sm) {
   assert(Sd < RegARM32::getNumSRegs());
   assert(Sn < RegARM32::getNumSRegs());
   assert(Sm < RegARM32::getNumSRegs());
   assert(CondARM32::isDefined(Cond));
   constexpr IValueT VFPOpcode = B27 | B26 | B25 | B11 | B9;
   const IValueT Encoding =
       Opcode | VFPOpcode | (encodeCondition(Cond) << kConditionShift) |
       (getYInRegXXXXY(Sd) << 22) | (getXXXXInRegXXXXY(Sn) << 16) |
       (getXXXXInRegXXXXY(Sd) << 12) | (getYInRegXXXXY(Sn) << 7) |
       (getYInRegXXXXY(Sm) << 5) | getXXXXInRegXXXXY(Sm);
   emitInst(Encoding);
 }
 
+void AssemblerARM32::emitVFPsss(CondARM32::Cond Cond, IValueT Opcode,
+                                const Operand *OpSd, const Operand *OpSn,
+                                const Operand *OpSm, const char *InstName) {
+  const IValueT Sd = encodeSRegister(OpSd, "Sd", InstName);
+  const IValueT Sn = encodeSRegister(OpSn, "Sn", InstName);
+  const IValueT Sm = encodeSRegister(OpSm, "Sm", InstName);
+  emitVFPsss(Cond, Opcode, Sd, Sn, Sm);
+}
+
 void AssemblerARM32::adc(const Operand *OpRd, const Operand *OpRn,
                          const Operand *OpSrc1, bool SetFlags,
                          CondARM32::Cond Cond) {
   // ADC (register) - ARM section 18.8.2, encoding A1:
   //   adc{s}<c> <Rd>, <Rn>, <Rm>{, <shift>}
   //
   // cccc0000101snnnnddddiiiiitt0mmmm where cccc=Cond, dddd=Rd, nnnn=Rn,
   // mmmm=Rm, iiiii=Shift, tt=ShiftKind, and s=SetFlags.
   //
   // ADC (Immediate) - ARM section A8.8.1, encoding A1:
@@ skipping 995 matching lines @@
 }
 
 void AssemblerARM32::vadds(const Operand *OpSd, const Operand *OpSn,
                            const Operand *OpSm, CondARM32::Cond Cond) {
   // VADD (floating-point) - ARM section A8.8.283, encoding A2:
   //   vadd<c>.f32 <Sd>, <Sn>, <Sm>
   //
   // cccc11100D11nnnndddd101sN0M0mmmm where cccc=Cond, s=0, ddddD=Rd, nnnnN=Rn,
   // and mmmmM=Rm.
   constexpr const char *Vadds = "vadds";
-  IValueT Sd = encodeSRegister(OpSd, "Sd", Vadds);
-  IValueT Sn = encodeSRegister(OpSn, "Sn", Vadds);
-  IValueT Sm = encodeSRegister(OpSm, "Sm", Vadds);
   constexpr IValueT VaddsOpcode = B21 | B20;
-  emitVFPsss(Cond, VaddsOpcode, Sd, Sn, Sm);
+  emitVFPsss(Cond, VaddsOpcode, OpSd, OpSn, OpSm, Vadds);
 }
 
 void AssemblerARM32::vaddd(const Operand *OpDd, const Operand *OpDn,
                            const Operand *OpDm, CondARM32::Cond Cond) {
   // VADD (floating-point) - ARM section A8.8.283, encoding A2:
   //   vadd<c>.f64 <Dd>, <Dn>, <Dm>
   //
   // cccc11100D11nnnndddd101sN0M0mmmm where cccc=Cond, s=1, Ddddd=Rd, Nnnnn=Rn,
   // and Mmmmm=Rm.
   constexpr const char *Vaddd = "vaddd";
-  IValueT Dd = encodeDRegister(OpDd, "Dd", Vaddd);
-  IValueT Dn = encodeDRegister(OpDn, "Dn", Vaddd);
-  IValueT Dm = encodeDRegister(OpDm, "Dm", Vaddd);
   constexpr IValueT VadddOpcode = B21 | B20;
-  emitVFPddd(Cond, VadddOpcode, Dd, Dn, Dm);
+  emitVFPddd(Cond, VadddOpcode, OpDd, OpDn, OpDm, Vaddd);
 }
 
 void AssemblerARM32::vcmpd(const Operand *OpDd, const Operand *OpDm,
                            CondARM32::Cond Cond) {
   constexpr const char *Vcmpd = "vcmpd";
   IValueT Dd = encodeDRegister(OpDd, "Dd", Vcmpd);
   IValueT Dm = encodeDRegister(OpDm, "Dm", Vcmpd);
   constexpr IValueT VcmpdOpcode = B23 | B21 | B20 | B18 | B6;
   constexpr IValueT Dn = 0;
   emitVFPddd(Cond, VcmpdOpcode, Dd, Dn, Dm);
@@ skipping 190 matching lines @@
 }
 
 void AssemblerARM32::vdivs(const Operand *OpSd, const Operand *OpSn,
                            const Operand *OpSm, CondARM32::Cond Cond) {
   // VDIV (floating-point) - ARM section A8.8.283, encoding A2:
   //   vdiv<c>.f32 <Sd>, <Sn>, <Sm>
   //
   // cccc11101D00nnnndddd101sN0M0mmmm where cccc=Cond, s=0, ddddD=Rd, nnnnN=Rn,
   // and mmmmM=Rm.
   constexpr const char *Vdivs = "vdivs";
-  IValueT Sd = encodeSRegister(OpSd, "Sd", Vdivs);
-  IValueT Sn = encodeSRegister(OpSn, "Sn", Vdivs);
-  IValueT Sm = encodeSRegister(OpSm, "Sm", Vdivs);
   constexpr IValueT VdivsOpcode = B23;
-  emitVFPsss(Cond, VdivsOpcode, Sd, Sn, Sm);
+  emitVFPsss(Cond, VdivsOpcode, OpSd, OpSn, OpSm, Vdivs);
 }
 
 void AssemblerARM32::vdivd(const Operand *OpDd, const Operand *OpDn,
                            const Operand *OpDm, CondARM32::Cond Cond) {
   // VDIV (floating-point) - ARM section A8.8.283, encoding A2:
   //   vdiv<c>.f64 <Dd>, <Dn>, <Dm>
   //
   // cccc11101D00nnnndddd101sN0M0mmmm where cccc=Cond, s=1, Ddddd=Rd, Nnnnn=Rn,
   // and Mmmmm=Rm.
   constexpr const char *Vdivd = "vdivd";
-  IValueT Dd = encodeDRegister(OpDd, "Dd", Vdivd);
-  IValueT Dn = encodeDRegister(OpDn, "Dn", Vdivd);
-  IValueT Dm = encodeDRegister(OpDm, "Dm", Vdivd);
   constexpr IValueT VdivdOpcode = B23;
-  emitVFPddd(Cond, VdivdOpcode, Dd, Dn, Dm);
+  emitVFPddd(Cond, VdivdOpcode, OpDd, OpDn, OpDm, Vdivd);
 }
 
 void AssemblerARM32::veord(const Operand *OpDd, const Operand *OpDn,
                            const Operand *OpDm) {
   // VEOR - ARM secdtion A8.8.315, encoding A1:
   //   veor<c> <Dd>, <Dn>, <Dm>
   //
   // 111100110D00nnnndddd0001N0M1mmmm where Ddddd=Dd, Nnnnn=Dn, and Mmmmm=Dm.
   constexpr const char *Veord = "veord";
   IValueT Dd = encodeDRegister(OpDd, "Dd", Veord);
@@ skipping 99 matching lines @@
   IValueT Rt = encodeGPRegister(OpRt, "Rt", Vmovsr);
   assert(Sn < RegARM32::getNumSRegs());
   assert(Rt < RegARM32::getNumGPRegs());
   assert(CondARM32::isDefined(Cond));
   IValueT Encoding = (encodeCondition(Cond) << kConditionShift) | B27 | B26 |
                      B25 | B11 | B9 | B4 | (getXXXXInRegXXXXY(Sn) << 16) |
                      (Rt << kRdShift) | (getYInRegXXXXY(Sn) << 7);
   emitInst(Encoding);
 }
 
+void AssemblerARM32::vmlad(const Operand *OpDd, const Operand *OpDn,
+                           const Operand *OpDm, CondARM32::Cond Cond) {
+  // VMLA, VMLS (floating-point), ARM section A8.8.337, encoding A2:
+  //   vmla<c>.f64 <Dd>, <Dn>, <Dm>
+  //
+  // cccc11100d00nnnndddd1011n0M0mmmm where cccc=Cond, Ddddd=Dd, Nnnnn=Dn, and
+  // Mmmmm=Dm
+  constexpr const char *Vmlad = "vmlad";
+  constexpr IValueT VmladOpcode = 0;
+  emitVFPddd(Cond, VmladOpcode, OpDd, OpDn, OpDm, Vmlad);
+}
+
+void AssemblerARM32::vmlas(const Operand *OpSd, const Operand *OpSn,
+                           const Operand *OpSm, CondARM32::Cond Cond) {
+  // VMLA, VMLS (floating-point), ARM section A8.8.337, encoding A2:
+  //   vmla<c>.f32 <Sd>, <Sn>, <Sm>
+  //
+  // cccc11100d00nnnndddd1010n0M0mmmm where cccc=Cond, ddddD=Sd, nnnnN=Sn, and
+  // mmmmM=Sm
+  constexpr const char *Vmlas = "vmlas";
+  constexpr IValueT VmlasOpcode = 0;
+  emitVFPsss(Cond, VmlasOpcode, OpSd, OpSn, OpSm, Vmlas);
+}
+
 void AssemblerARM32::vmrsAPSR_nzcv(CondARM32::Cond Cond) {
   // MVRS - ARM section A*.8.348, encoding A1:
   //   vmrs<c> APSR_nzcv, FPSCR
   //
   // cccc111011110001tttt101000010000 where tttt=0x15 (i.e. when Rt=pc, use
   // APSR_nzcv instead).
   assert(CondARM32::isDefined(Cond));
   IValueT Encoding = B27 | B26 | B25 | B23 | B22 | B21 | B20 | B16 | B15 | B14 |
                      B13 | B12 | B11 | B9 | B4 |
                      (encodeCondition(Cond) << kConditionShift);
   emitInst(Encoding);
 }
 
 void AssemblerARM32::vmuls(const Operand *OpSd, const Operand *OpSn,
                            const Operand *OpSm, CondARM32::Cond Cond) {
   // VMUL (floating-point) - ARM section A8.8.351, encoding A2:
   //   vmul<c>.f32 <Sd>, <Sn>, <Sm>
   //
   // cccc11100D10nnnndddd101sN0M0mmmm where cccc=Cond, s=0, ddddD=Rd, nnnnN=Rn,
   // and mmmmM=Rm.
   constexpr const char *Vmuls = "vmuls";
-  IValueT Sd = encodeSRegister(OpSd, "Sd", Vmuls);
-  IValueT Sn = encodeSRegister(OpSn, "Sn", Vmuls);
-  IValueT Sm = encodeSRegister(OpSm, "Sm", Vmuls);
   constexpr IValueT VmulsOpcode = B21;
-  emitVFPsss(Cond, VmulsOpcode, Sd, Sn, Sm);
+  emitVFPsss(Cond, VmulsOpcode, OpSd, OpSn, OpSm, Vmuls);
 }
 
 void AssemblerARM32::vmuld(const Operand *OpDd, const Operand *OpDn,
                            const Operand *OpDm, CondARM32::Cond Cond) {
   // VMUL (floating-point) - ARM section A8.8.351, encoding A2:
   //   vmul<c>.f64 <Dd>, <Dn>, <Dm>
   //
   // cccc11100D10nnnndddd101sN0M0mmmm where cccc=Cond, s=1, Ddddd=Rd, Nnnnn=Rn,
   // and Mmmmm=Rm.
   constexpr const char *Vmuld = "vmuld";
-  IValueT Dd = encodeDRegister(OpDd, "Dd", Vmuld);
-  IValueT Dn = encodeDRegister(OpDn, "Dn", Vmuld);
-  IValueT Dm = encodeDRegister(OpDm, "Dm", Vmuld);
   constexpr IValueT VmuldOpcode = B21;
-  emitVFPddd(Cond, VmuldOpcode, Dd, Dn, Dm);
+  emitVFPddd(Cond, VmuldOpcode, OpDd, OpDn, OpDm, Vmuld);
 }
 
 void AssemblerARM32::vstrd(const Operand *OpDd, const Operand *OpAddress,
                            CondARM32::Cond Cond, const TargetInfo &TInfo) {
   // VSTR - ARM section A8.8.413, encoding A1:
   //   vstr<c> <Dd>, [<Rn>{, #+/-<Imm>}]
   //
   // cccc1101UD00nnnndddd1011iiiiiiii where cccc=Cond, nnnn=Rn, Ddddd=Rd,
   // iiiiiiii=abs(Imm >> 2), and U=1 if Imm>=0.
   constexpr const char *Vstrd = "vstrd";
@@ skipping 33 matching lines @@
 }
 
 void AssemblerARM32::vsubs(const Operand *OpSd, const Operand *OpSn,
                            const Operand *OpSm, CondARM32::Cond Cond) {
   // VSUB (floating-point) - ARM section A8.8.415, encoding A2:
   //   vsub<c>.f32 <Sd>, <Sn>, <Sm>
   //
   // cccc11100D11nnnndddd101sN1M0mmmm where cccc=Cond, s=0, ddddD=Rd, nnnnN=Rn,
   // and mmmmM=Rm.
   constexpr const char *Vsubs = "vsubs";
-  IValueT Sd = encodeSRegister(OpSd, "Sd", Vsubs);
-  IValueT Sn = encodeSRegister(OpSn, "Sn", Vsubs);
-  IValueT Sm = encodeSRegister(OpSm, "Sm", Vsubs);
   constexpr IValueT VsubsOpcode = B21 | B20 | B6;
-  emitVFPsss(Cond, VsubsOpcode, Sd, Sn, Sm);
+  emitVFPsss(Cond, VsubsOpcode, OpSd, OpSn, OpSm, Vsubs);
 }
 
 void AssemblerARM32::vsubd(const Operand *OpDd, const Operand *OpDn,
                            const Operand *OpDm, CondARM32::Cond Cond) {
   // VSUB (floating-point) - ARM section A8.8.415, encoding A2:
   //   vsub<c>.f64 <Dd>, <Dn>, <Dm>
   //
   // cccc11100D11nnnndddd101sN1M0mmmm where cccc=Cond, s=1, Ddddd=Rd, Nnnnn=Rn,
   // and Mmmmm=Rm.
   constexpr const char *Vsubd = "vsubd";
-  IValueT Dd = encodeDRegister(OpDd, "Dd", Vsubd);
-  IValueT Dn = encodeDRegister(OpDn, "Dn", Vsubd);
-  IValueT Dm = encodeDRegister(OpDm, "Dm", Vsubd);
   constexpr IValueT VsubdOpcode = B21 | B20 | B6;
-  emitVFPddd(Cond, VsubdOpcode, Dd, Dn, Dm);
+  emitVFPddd(Cond, VsubdOpcode, OpDd, OpDn, OpDm, Vsubd);
 }
 
 void AssemblerARM32::emitVStackOp(CondARM32::Cond Cond, IValueT Opcode,
                                   const Variable *OpBaseReg,
                                   SizeT NumConsecRegs) {
   const IValueT BaseReg = getEncodedSRegNum(OpBaseReg);
   const IValueT DLastBit = mask(BaseReg, 0, 1); // Last bit of base register.
   const IValueT Rd = mask(BaseReg, 1, 4);       // Top 4 bits of base register.
   assert(0 < NumConsecRegs);
   (void)VpushVpopMaxConsecRegs;
@@ skipping 30 matching lines @@
   //
   // cccc11010D101101dddd1010iiiiiiii where cccc=Cond, ddddD=BaseReg, and
   // iiiiiiii=NumConsecRegs.
   constexpr IValueT VpushOpcode =
       B27 | B26 | B24 | B21 | B19 | B18 | B16 | B11 | B9;
   emitVStackOp(Cond, VpushOpcode, OpBaseReg, NumConsecRegs);
 }
 
 } // end of namespace ARM32
 } // end of namespace Ice