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| 1 // Copyright (c) 2013, the Dart project authors. Please see the AUTHORS file | 1 // Copyright (c) 2013, the Dart project authors. Please see the AUTHORS file |
| 2 // for details. All rights reserved. Use of this source code is governed by a | 2 // for details. All rights reserved. Use of this source code is governed by a |
| 3 // BSD-style license that can be found in the LICENSE file. | 3 // BSD-style license that can be found in the LICENSE file. |
| 4 // | 4 // |
| 5 // This is forked from Dart revision df52deea9f25690eb8b66c5995da92b70f7ac1fe | 5 // This is forked from Dart revision df52deea9f25690eb8b66c5995da92b70f7ac1fe |
| 6 // Please update the (git) revision if we merge changes from Dart. | 6 // Please update the (git) revision if we merge changes from Dart. |
| 7 // https://code.google.com/p/dart/wiki/GettingTheSource | 7 // https://code.google.com/p/dart/wiki/GettingTheSource |
| 8 | 8 |
| 9 #include "vm/globals.h" // NOLINT | 9 #include "vm/globals.h" // NOLINT |
| 10 #if defined(TARGET_ARCH_ARM) | 10 #if defined(TARGET_ARCH_ARM) |
| (...skipping 959 matching lines...) Expand 10 before | Expand all | Expand 10 after Loading... |
| 970 Condition cond) { | 970 Condition cond) { |
| 971 EmitVFPsss(cond, B21 | B20, sd, sn, sm); | 971 EmitVFPsss(cond, B21 | B20, sd, sn, sm); |
| 972 } | 972 } |
| 973 | 973 |
| 974 // Moved to Arm32::AssemblerARM32::vaddd() | 974 // Moved to Arm32::AssemblerARM32::vaddd() |
| 975 void Assembler::vaddd(DRegister dd, DRegister dn, DRegister dm, | 975 void Assembler::vaddd(DRegister dd, DRegister dn, DRegister dm, |
| 976 Condition cond) { | 976 Condition cond) { |
| 977 EmitVFPddd(cond, B21 | B20, dd, dn, dm); | 977 EmitVFPddd(cond, B21 | B20, dd, dn, dm); |
| 978 } | 978 } |
| 979 | 979 |
| 980 // Moved to Arm32::AssemblerARM32::vmuls() | 980 // Moved to Arm32::AssemblerARM32::vsubs() |
| 981 void Assembler::vsubs(SRegister sd, SRegister sn, SRegister sm, | 981 void Assembler::vsubs(SRegister sd, SRegister sn, SRegister sm, |
| 982 Condition cond) { | 982 Condition cond) { |
| 983 EmitVFPsss(cond, B21 | B20 | B6, sd, sn, sm); | 983 EmitVFPsss(cond, B21 | B20 | B6, sd, sn, sm); |
| 984 } | 984 } |
| 985 | 985 |
| 986 // Moved to Arm32::AssemblerARM32::vmuld() | 986 // Moved to Arm32::AssemblerARM32::vsubd() |
| 987 void Assembler::vsubd(DRegister dd, DRegister dn, DRegister dm, | 987 void Assembler::vsubd(DRegister dd, DRegister dn, DRegister dm, |
| 988 Condition cond) { | 988 Condition cond) { |
| 989 EmitVFPddd(cond, B21 | B20 | B6, dd, dn, dm); | 989 EmitVFPddd(cond, B21 | B20 | B6, dd, dn, dm); |
| 990 } | 990 } |
| 991 #endif | |
| 992 | 991 |
| 993 #if 0 | 992 // Moved to Arm32::AssemblerARM32::vmuls() |
| 994 void Assembler::vmuls(SRegister sd, SRegister sn, SRegister sm, | 993 void Assembler::vmuls(SRegister sd, SRegister sn, SRegister sm, |
| 995 Condition cond) { | 994 Condition cond) { |
| 996 EmitVFPsss(cond, B21, sd, sn, sm); | 995 EmitVFPsss(cond, B21, sd, sn, sm); |
| 997 } | 996 } |
| 998 | 997 |
| 999 | 998 // Moved to Arm32::AssemblerARM32::vmuld() |
| 1000 void Assembler::vmuld(DRegister dd, DRegister dn, DRegister dm, | 999 void Assembler::vmuld(DRegister dd, DRegister dn, DRegister dm, |
| 1001 Condition cond) { | 1000 Condition cond) { |
| 1002 EmitVFPddd(cond, B21, dd, dn, dm); | 1001 EmitVFPddd(cond, B21, dd, dn, dm); |
| 1003 } | 1002 } |
| 1004 #endif | |
| 1005 | 1003 |
| 1004 // Moved to Arm32::AssemblerARM32::vmlas() |
| 1006 void Assembler::vmlas(SRegister sd, SRegister sn, SRegister sm, | 1005 void Assembler::vmlas(SRegister sd, SRegister sn, SRegister sm, |
| 1007 Condition cond) { | 1006 Condition cond) { |
| 1008 EmitVFPsss(cond, 0, sd, sn, sm); | 1007 EmitVFPsss(cond, 0, sd, sn, sm); |
| 1009 } | 1008 } |
| 1010 | 1009 |
| 1011 | 1010 // Moved to Arm32::AssemblerARM32::vmlad() |
| 1012 void Assembler::vmlad(DRegister dd, DRegister dn, DRegister dm, | 1011 void Assembler::vmlad(DRegister dd, DRegister dn, DRegister dm, |
| 1013 Condition cond) { | 1012 Condition cond) { |
| 1014 EmitVFPddd(cond, 0, dd, dn, dm); | 1013 EmitVFPddd(cond, 0, dd, dn, dm); |
| 1015 } | 1014 } |
| 1015 #endif |
| 1016 | 1016 |
| 1017 | 1017 |
| 1018 void Assembler::vmlss(SRegister sd, SRegister sn, SRegister sm, | 1018 void Assembler::vmlss(SRegister sd, SRegister sn, SRegister sm, |
| 1019 Condition cond) { | 1019 Condition cond) { |
| 1020 EmitVFPsss(cond, B6, sd, sn, sm); | 1020 EmitVFPsss(cond, B6, sd, sn, sm); |
| 1021 } | 1021 } |
| 1022 | 1022 |
| 1023 | 1023 |
| 1024 void Assembler::vmlsd(DRegister dd, DRegister dn, DRegister dm, | 1024 void Assembler::vmlsd(DRegister dd, DRegister dn, DRegister dm, |
| 1025 Condition cond) { | 1025 Condition cond) { |
| (...skipping 2662 matching lines...) Expand 10 before | Expand all | Expand 10 after Loading... |
| 3688 | 3688 |
| 3689 | 3689 |
| 3690 const char* Assembler::FpuRegisterName(FpuRegister reg) { | 3690 const char* Assembler::FpuRegisterName(FpuRegister reg) { |
| 3691 ASSERT((0 <= reg) && (reg < kNumberOfFpuRegisters)); | 3691 ASSERT((0 <= reg) && (reg < kNumberOfFpuRegisters)); |
| 3692 return fpu_reg_names[reg]; | 3692 return fpu_reg_names[reg]; |
| 3693 } | 3693 } |
| 3694 | 3694 |
| 3695 } // namespace dart | 3695 } // namespace dart |
| 3696 | 3696 |
| 3697 #endif // defined TARGET_ARCH_ARM | 3697 #endif // defined TARGET_ARCH_ARM |
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