Add VMLA (floating point) to the integrated ARM assembler.

src/IceAssemblerARM32.h

 //===- subzero/src/IceAssemblerARM32.h - Assembler for ARM32 ----*- C++ -*-===//
 //
 // Copyright (c) 2013, the Dart project authors.  Please see the AUTHORS file
 // for details. All rights reserved. Use of this source code is governed by a
 // BSD-style license that can be found in the LICENSE file.
 //
 // Modified by the Subzero authors.
 //
 //===----------------------------------------------------------------------===//
 //
@@ skipping 366 matching lines @@
              CondARM32::Cond Cond, const TargetInfo &TInfo);
 
   void vldrs(const Operand *OpSd, const Operand *OpAddress,
              CondARM32::Cond Cond, const TargetLowering *Lowering) {
     const TargetInfo TInfo(Lowering);
     vldrs(OpSd, OpAddress, Cond, TInfo);
   }
 
   void vmovsr(const Operand *OpSn, const Operand *OpRt, CondARM32::Cond Cond);
 
+  void vmlad(const Operand *OpDd, const Operand *OpDn, const Operand *OpDm,
+             CondARM32::Cond Cond);
+
+  void vmlas(const Operand *OpSd, const Operand *OpSn, const Operand *OpSm,
+             CondARM32::Cond Cond);
+
   // Uses APSR_nzcv as register
   void vmrsAPSR_nzcv(CondARM32::Cond Cond);
 
   void vmuld(const Operand *OpDd, const Operand *OpDn, const Operand *OpDm,
              CondARM32::Cond Cond);
 
   void vmuls(const Operand *OpSd, const Operand *OpSn, const Operand *OpSm,
              CondARM32::Cond Cond);
 
   void vpop(const Variable *OpBaseReg, SizeT NumConsecRegs,
@@ skipping 175 matching lines @@
   // Returns the offset encoded in the branch instruction Inst.
   static IOffsetT decodeBranchOffset(IValueT Inst);
 
   // Implements movw/movt, generating pattern ccccxxxxxxxsiiiiddddiiiiiiiiiiii
   // where cccc=Cond, xxxxxxx<<21=Opcode, dddd=Rd, s=SetFlags, and
   // iiiiiiiiiiiiiiii=Imm16.
   void emitMovwt(CondARM32::Cond Cond, bool IsMovw, const Operand *OpRd,
                  const Operand *OpSrc, const char *MovName);
 
   // Emit VFP instruction with 3 D registers.
+  void emitVFPddd(CondARM32::Cond Cond, IValueT Opcode, const Operand *OpDd,
+                  const Operand *OpDn, const Operand *OpDm,
+                  const char *InstName);
+
   void emitVFPddd(CondARM32::Cond Cond, IValueT Opcode, IValueT Dd, IValueT Dn,
                   IValueT Dm);
 
   // Emit VFP instruction with 3 S registers.
   void emitVFPsss(CondARM32::Cond Cond, IValueT Opcode, IValueT Sd, IValueT Sn,
                   IValueT Sm);
+
+  void emitVFPsss(CondARM32::Cond Cond, IValueT Opcode, const Operand *OpSd,
+                  const Operand *OpSn, const Operand *OpSm,
+                  const char *InstName);
 };
 
 } // end of namespace ARM32
 } // end of namespace Ice
 
 #endif // SUBZERO_SRC_ICEASSEMBLERARM32_H