Clean up register+immediate addresses in ARM.

src/IceAssemblerARM32.cpp

 //===- subzero/src/IceAssemblerARM32.cpp - Assembler for ARM32 --*- C++ -*-===//
 //
 // Copyright (c) 2013, the Dart project authors.  Please see the AUTHORS file
 // for details. All rights reserved. Use of this source code is governed by a
 // BSD-style license that can be found in the LICENSE file.
 //
 // Modified by the Subzero authors.
 //
 //===----------------------------------------------------------------------===//
 //
@@ skipping 157 matching lines @@
 }
 
 // Extract out a Bit in Value.
 bool isBitSet(IValueT Bit, IValueT Value) { return (Value & Bit) == Bit; }
 
 // Returns the GPR register at given Shift in Value.
 RegARM32::GPRRegister getGPRReg(IValueT Shift, IValueT Value) {
   return decodeGPRRegister((Value >> Shift) & 0xF);
 }
 
-// Defines alternate layouts of instruction operands, should the (common)
-// default pattern not be used.
-enum OpEncoding {
-  // No alternate layout specified.
-  DefaultOpEncoding,
-  // Alternate encoding for ImmRegOffset, where the offset is divided by 4
-  // before encoding.
-  ImmRegOffsetDiv4,
-  // Alternate encoding 3 for memory operands (like in strb, strh, ldrb, and
-  // ldrh.
-  OpEncoding3,
-  // Alternate encoding for memory operands for ldrex and strex, which only
-  // actually expect a register.
-  OpEncodingMemEx
-};
-
 IValueT getEncodedGPRegNum(const Variable *Var) {
   assert(Var->hasReg());
   int32_t Reg = Var->getRegNum();
   return llvm::isa<Variable64On32>(Var) ? RegARM32::getI64PairFirstGPRNum(Reg)
                                         : RegARM32::getEncodedGPR(Reg);
 }
 
 IValueT getEncodedSRegNum(const Variable *Var) {
   assert(Var->hasReg());
   return RegARM32::getEncodedSReg(Var->getRegNum());
 }
 
 IValueT getEncodedDRegNum(const Variable *Var) {
   return RegARM32::getEncodedDReg(Var->getRegNum());
 }
 
 IValueT getYInRegXXXXY(IValueT RegXXXXY) { return RegXXXXY & 0x1; }
 
 IValueT getXXXXInRegXXXXY(IValueT RegXXXXY) { return RegXXXXY >> 1; }
 
 IValueT getYInRegYXXXX(IValueT RegYXXXX) { return RegYXXXX >> 4; }
 
 IValueT getXXXXInRegYXXXX(IValueT RegYXXXX) { return RegYXXXX & 0x0f; }
 
+// Defines layouts of an operand representing a (register) memory address,
+// possibly modified by an immediate value.
+enum EncodedImmAddress {
+  // Address modified by a rotated immediate 8-bit value.
+  RotatedImm8Address,
+  // Alternate encoding for RotatedImm8Address, where the offset is divided by 4

[Jim Stichnoth, 2016/01/25 20:37:50]

Optional: Consider adding a blank line after each enum value, to make it easier
to associate the comment with the correct enum value.

[Karl, 2016/01/25 23:59:16]

Added blank lines. Did same for following enum EncodedOperand.

+  // before encoding.
+  RotatedImm8Div4Address,
+  // Address modified by an immediate 12-bit value.
+  Imm12Address,
+  // Alternate encoding 3, for an address modified by a rotated immediate 8-bit
+  // value.
+  RotatedImm8Enc3Address,
+  // Encoding where no immediate offset is used.
+  NoImmOffsetAddress
+};
+
 // The way an operand is encoded into a sequence of bits in functions
 // encodeOperand and encodeAddress below.
 enum EncodedOperand {
   // Unable to encode, value left undefined.
   CantEncode = 0,
   // Value is register found.
   EncodedAsRegister,
   // Value=rrrriiiiiiii where rrrr is the rotation, and iiiiiiii is the imm8
   // value.
   EncodedAsRotatedImm8,
   // EncodedAsImmRegOffset is a memory operand that can take three forms, based
-  // on OpEncoding:
+  // on type EncodedImmAddress:
   //
-  // ***** DefaultOpEncoding *****
+  // ***** RotatedImm8Address *****
   //
   // Value=0000000pu0w0nnnn0000iiiiiiiiiiii where nnnn is the base register Rn,
   // p=1 if pre-indexed addressing, u=1 if offset positive, w=1 if writeback to
   // Rn should be used, and iiiiiiiiiiii defines the rotated Imm8 value.
   //
-  // ***** OpEncoding3 *****
+  // ***** RotatedImm8Div4Address *****
   //
   // Value=00000000pu0w0nnnn0000iiii0000jjjj where nnnn=Rn, iiiijjjj=Imm8, p=1
   // if pre-indexed addressing, u=1 if offset positive, and w=1 if writeback to
   // Rn.
   //
-  // ***** OpEncodingMemEx *****
+  // ***** Imm12Address *****
   //
-  // Value=00000000U000nnnn00000000xxxxxxxx where nnnn=Rn, xxxxxxxx=abs(Offset),
-  // and U=1 Offset>=0.
+  // Value=0000000pu0w0nnnn0000iiiiiiiiiiii where nnnn is the base register Rn,
+  // p=1 if pre-indexed addressing, u=1 if offset positive, w=1 if writeback to
+  // Rn should be used, and iiiiiiiiiiii defines the immediate 12-bit value.
+  //
+  // ***** NoImmOffsetAddress *****
+  //
+  // Value=000000001000nnnn0000000000000000 where nnnn=Rn.
   EncodedAsImmRegOffset,
   // Value=0000000pu0w00nnnnttttiiiiiss0mmmm where nnnn is the base register Rn,
   // mmmm is the index register Rm, iiiii is the shift amount, ss is the shift
   // kind, p=1 if pre-indexed addressing, u=1 if offset positive, and w=1 if
   // writeback to Rn.
   EncodedAsShiftRotateImm5,
   // Value=000000000000000000000iiiii0000000 where iiii defines the Imm5 value
   // to shift.
   EncodedAsShiftImm5,
   // Value=iiiiiss0mmmm where mmmm is the register to rotate, ss is the shift
@@ skipping 92 matching lines @@
   }
   if (const auto *ShImm = llvm::dyn_cast<OperandARM32ShAmtImm>(Opnd)) {
     const IValueT Immed5 = ShImm->getShAmtImm();
     assert(Immed5 < (1 << kShiftImmBits));
     Value = (Immed5 << kShiftImmShift);
     return EncodedAsShiftImm5;
   }
   return CantEncode;
 }
 
-IValueT encodeImmRegOffset(IValueT Reg, IOffsetT Offset,
-                           OperandARM32Mem::AddrMode Mode,
-                           IValueT OffsetShift = 0) {
+inline IValueT encodeImmRegOffset(IValueT Reg, IOffsetT Offset,

[Jim Stichnoth, 2016/01/25 20:37:50]

Why inline here?  This seems inconsistent with the other functions here.

[Karl, 2016/01/25 23:59:16]

Removed.

+                                  OperandARM32Mem::AddrMode Mode,
+                                  IOffsetT MaxOffset, IValueT OffsetShift) {
   IValueT Value = Mode | (Reg << kRnShift);
   if (Offset < 0) {
     Offset = -Offset;
     Value ^= U; // Flip U to adjust sign.
   }
+  assert(Offset <= MaxOffset);
+  (void)MaxOffset;
   return Value | (Offset >> OffsetShift);
 }
 
 // Encodes immediate register offset using encoding 3.
 IValueT encodeImmRegOffsetEnc3(IValueT Rn, IOffsetT Imm8,
                                OperandARM32Mem::AddrMode Mode) {
   IValueT Value = Mode | (Rn << kRnShift);
   if (Imm8 < 0) {
     Imm8 = -Imm8;
     Value = (Value ^ U);
   }
   assert(Imm8 < (1 << 8));
   Value = Value | B22 | ((Imm8 & 0xf0) << 4) | (Imm8 & 0x0f);
   return Value;
 }
 
-IValueT encodeImmRegOffset(OpEncoding AddressEncoding, IValueT Reg,
+IValueT encodeImmRegOffset(EncodedImmAddress ImmEncoding, IValueT Reg,
                            IOffsetT Offset, OperandARM32Mem::AddrMode Mode) {
-  switch (AddressEncoding) {
-  case DefaultOpEncoding:
-    return encodeImmRegOffset(Reg, Offset, Mode);
-  case ImmRegOffsetDiv4: {
+  switch (ImmEncoding) {
+  case RotatedImm8Address: {
+    constexpr IOffsetT MaxOffset = (1 << 8) - 1;
+    constexpr IValueT NoRightShift = 0;
+    return encodeImmRegOffset(Reg, Offset, Mode, MaxOffset, NoRightShift);
+  }
+  case RotatedImm8Div4Address: {
     assert((Offset & 0x3) == 0);
+    constexpr IOffsetT MaxOffset = (1 << 8) - 1;
     constexpr IValueT RightShift2 = 2;
-    return encodeImmRegOffset(Reg, Offset, Mode, RightShift2);
+    return encodeImmRegOffset(Reg, Offset, Mode, MaxOffset, RightShift2);
   }
-  case OpEncoding3:
+  case Imm12Address: {
+    constexpr IOffsetT MaxOffset = (1 << 12) - 1;
+    constexpr IValueT NoRightShift = 0;
+    return encodeImmRegOffset(Reg, Offset, Mode, MaxOffset, NoRightShift);
+  }
+  case RotatedImm8Enc3Address:
     return encodeImmRegOffsetEnc3(Reg, Offset, Mode);
-  case OpEncodingMemEx:
+  case NoImmOffsetAddress: {
     assert(Offset == 0);
     assert(Mode == OperandARM32Mem::Offset);
     return Reg << kRnShift;
   }
+  }
   llvm_unreachable("(silence g++ warning)");
 }
 
 // Encodes memory address Opnd, and encodes that information into Value, based
 // on how ARM represents the address. Returns how the value was encoded.
 EncodedOperand encodeAddress(const Operand *Opnd, IValueT &Value,
                              const AssemblerARM32::TargetInfo &TInfo,
-                             OpEncoding AddressEncoding = DefaultOpEncoding) {
+                             EncodedImmAddress ImmEncoding) {
   Value = 0; // Make sure initialized.
   if (const auto *Var = llvm::dyn_cast<Variable>(Opnd)) {
     // Should be a stack variable, with an offset.
     if (Var->hasReg())
       return CantEncode;
     IOffsetT Offset = Var->getStackOffset();
     if (!Utils::IsAbsoluteUint(12, Offset))
       return CantEncode;
     int32_t BaseRegNum = Var->getBaseRegNum();
     if (BaseRegNum == Variable::NoRegister)
       BaseRegNum = TInfo.FrameOrStackReg;
-    Value = encodeImmRegOffset(AddressEncoding, BaseRegNum, Offset,
+    Value = encodeImmRegOffset(ImmEncoding, BaseRegNum, Offset,
                                OperandARM32Mem::Offset);
     return EncodedAsImmRegOffset;
   }
   if (const auto *Mem = llvm::dyn_cast<OperandARM32Mem>(Opnd)) {
     Variable *Var = Mem->getBase();
     if (!Var->hasReg())
       return CantEncode;
     IValueT Rn = getEncodedGPRegNum(Var);
     if (Mem->isRegReg()) {
       const Variable *Index = Mem->getIndex();
       if (Var == nullptr)
         return CantEncode;
       Value = (Rn << kRnShift) | Mem->getAddrMode() |
               encodeShiftRotateImm5(getEncodedGPRegNum(Index),
                                     Mem->getShiftOp(), Mem->getShiftAmt());
       return EncodedAsShiftRotateImm5;
     }
     // Encoded as immediate register offset.
     ConstantInteger32 *Offset = Mem->getOffset();
-    Value = encodeImmRegOffset(AddressEncoding, Rn, Offset->getValue(),
+    Value = encodeImmRegOffset(ImmEncoding, Rn, Offset->getValue(),
                                Mem->getAddrMode());
     return EncodedAsImmRegOffset;
   }
   return CantEncode;
 }
 
 // Checks that Offset can fit in imm24 constant of branch (b) instruction.
 bool canEncodeBranchOffset(IOffsetT Offset) {
   return Utils::IsAligned(Offset, 4) &&
          Utils::IsInt(kBranchOffsetBits, Offset >> 2);
@@ skipping 345 matching lines @@
   const IValueT Encoding = (encodeCondition(Cond) << kConditionShift) |
                            (InstType << kTypeShift) | (IsLoad ? L : 0) |
                            (IsByte ? B : 0) | (Rt << kRdShift) | Address;
   emitInst(Encoding);
 }
 
 void AssemblerARM32::emitMemOp(CondARM32::Cond Cond, bool IsLoad, bool IsByte,
                                IValueT Rt, const Operand *OpAddress,
                                const TargetInfo &TInfo, const char *InstName) {
   IValueT Address;
-  switch (encodeAddress(OpAddress, Address, TInfo)) {
+  switch (encodeAddress(OpAddress, Address, TInfo, Imm12Address)) {
   default:
     llvm::report_fatal_error(std::string(InstName) +
                              ": Memory address not understood");
   case EncodedAsImmRegOffset: {
     // XXX{B} (immediate):
     //   xxx{b}<c> <Rt>, [<Rn>{, #+/-<imm12>}]      ; p=1, w=0
     //   xxx{b}<c> <Rt>, [<Rn>], #+/-<imm12>        ; p=1, w=1
     //   xxx{b}<c> <Rt>, [<Rn>, #+/-<imm12>]!       ; p=0, w=1
     //
     // cccc010pubwlnnnnttttiiiiiiiiiiii where cccc=Cond, tttt=Rt, nnnn=Rn,
@@ skipping 37 matching lines @@
     return;
   }
   }
 }
 
 void AssemblerARM32::emitMemOpEnc3(CondARM32::Cond Cond, IValueT Opcode,
                                    IValueT Rt, const Operand *OpAddress,
                                    const TargetInfo &TInfo,
                                    const char *InstName) {
   IValueT Address;
-  switch (encodeAddress(OpAddress, Address, TInfo, OpEncoding3)) {
+  switch (encodeAddress(OpAddress, Address, TInfo, RotatedImm8Enc3Address)) {
   default:
     llvm::report_fatal_error(std::string(InstName) +
                              ": Memory address not understood");
   case EncodedAsImmRegOffset: {
     // XXXH (immediate)
     //   xxxh<c> <Rt>, [<Rn>{, #+-<Imm8>}]
     //   xxxh<c> <Rt>, [<Rn>, #+/-<Imm8>]
     //   xxxh<c> <Rt>, [<Rn>, #+/-<Imm8>]!
     //
     // cccc000pu0wxnnnnttttiiiiyyyyjjjj where cccc=Cond, nnnn=Rn, tttt=Rt,
@@ skipping 475 matching lines @@
     break;
   case IceType_i16:
     MemExOpcode |= B2 | B1;
     break;
   case IceType_i32:
     break;
   case IceType_i64:
     MemExOpcode |= B1;
   }
   IValueT AddressRn;
-  if (encodeAddress(OpAddress, AddressRn, TInfo, OpEncodingMemEx) !=
+  if (encodeAddress(OpAddress, AddressRn, TInfo, NoImmOffsetAddress) !=
       EncodedAsImmRegOffset)
     llvm::report_fatal_error(std::string(InstName) +
                              ": Can't extract Rn from address");
   assert(Utils::IsAbsoluteUint(3, MemExOpcode));
   assert(Rd < RegARM32::getNumGPRegs());
   assert(Rt < RegARM32::getNumGPRegs());
   assert(CondARM32::isDefined(Cond));
   IValueT Encoding = (Cond << kConditionShift) | B24 | B23 | B11 | B10 | B9 |
                      B8 | B7 | B4 | (MemExOpcode << kMemExOpcodeShift) |
                      AddressRn | (Rd << kRdShift) | (Rt << kRmShift);
@@ skipping 353 matching lines @@
   // POP - ARM section A8.8.132, encoding A2:
   //   pop<c> {Rt}
   //
   // cccc010010011101dddd000000000100 where dddd=Rt and cccc=Cond.
   constexpr const char *Pop = "pop";
   IValueT Rt = encodeGPRegister(OpRt, "Rt", Pop);
   verifyRegsNotEq(Rt, "Rt", RegARM32::Encoded_Reg_sp, "sp", Pop);
   // Same as load instruction.
   constexpr bool IsLoad = true;
   constexpr bool IsByte = false;
-  IValueT Address = encodeImmRegOffset(RegARM32::Encoded_Reg_sp, kWordSize,
-                                       OperandARM32Mem::PostIndex);
+  constexpr IOffsetT MaxOffset = (1 << 8) - 1;
+  constexpr IValueT NoShiftRight = 0;
+  IValueT Address =
+      encodeImmRegOffset(RegARM32::Encoded_Reg_sp, kWordSize,
+                         OperandARM32Mem::PostIndex, MaxOffset, NoShiftRight);
   emitMemOp(Cond, kInstTypeMemImmediate, IsLoad, IsByte, Rt, Address);
 }
 
 void AssemblerARM32::popList(const IValueT Registers, CondARM32::Cond Cond) {
   // POP - ARM section A8.*.131, encoding A1:
   //   pop<c> <registers>
   //
   // cccc100010111101rrrrrrrrrrrrrrrr where cccc=Cond and
   // rrrrrrrrrrrrrrrr=Registers (one bit for each GP register).
   constexpr bool IsLoad = true;
   emitMultiMemOp(Cond, IA_W, IsLoad, RegARM32::Encoded_Reg_sp, Registers);
 }
 
 void AssemblerARM32::push(const Operand *OpRt, CondARM32::Cond Cond) {
   // PUSH - ARM section A8.8.133, encoding A2:
   //   push<c> {Rt}
   //
   // cccc010100101101dddd000000000100 where dddd=Rt and cccc=Cond.
   constexpr const char *Push = "push";
   IValueT Rt = encodeGPRegister(OpRt, "Rt", Push);
   verifyRegsNotEq(Rt, "Rt", RegARM32::Encoded_Reg_sp, "sp", Push);
   // Same as store instruction.
   constexpr bool isLoad = false;
   constexpr bool isByte = false;
-  IValueT Address = encodeImmRegOffset(RegARM32::Encoded_Reg_sp, -kWordSize,
-                                       OperandARM32Mem::PreIndex);
+  constexpr IOffsetT MaxOffset = (1 << 8) - 1;
+  constexpr IValueT NoShiftRight = 0;
+  IValueT Address =
+      encodeImmRegOffset(RegARM32::Encoded_Reg_sp, -kWordSize,
+                         OperandARM32Mem::PreIndex, MaxOffset, NoShiftRight);
   emitMemOp(Cond, kInstTypeMemImmediate, isLoad, isByte, Rt, Address);
 }
 
 void AssemblerARM32::pushList(const IValueT Registers, CondARM32::Cond Cond) {
   // PUSH - ARM section A8.8.133, encoding A1:
   //   push<c> <Registers>
   //
   // cccc100100101101rrrrrrrrrrrrrrrr where cccc=Cond and
   // rrrrrrrrrrrrrrrr=Registers (one bit for each GP register).
   constexpr bool IsLoad = false;
@@ skipping 544 matching lines @@
   // VLDR - ARM section A8.8.333, encoding A1.
   //   vldr<c> <Dd>, [<Rn>{, #+/-<imm>}]
   //
   // cccc1101UD01nnnndddd1011iiiiiiii where cccc=Cond, nnnn=Rn, Ddddd=Rd,
   // iiiiiiii=abs(Imm >> 2), and U=1 if Opcode>=0.
   constexpr const char *Vldrd = "vldrd";
   IValueT Dd = encodeDRegister(OpDd, "Dd", Vldrd);
   assert(CondARM32::isDefined(Cond));
   IValueT Address;
   EncodedOperand AddressEncoding =
-      encodeAddress(OpAddress, Address, TInfo, ImmRegOffsetDiv4);
+      encodeAddress(OpAddress, Address, TInfo, RotatedImm8Div4Address);
   (void)AddressEncoding;
   assert(AddressEncoding == EncodedAsImmRegOffset);
   IValueT Encoding = B27 | B26 | B24 | B20 | B11 | B9 | B8 |
                      (encodeCondition(Cond) << kConditionShift) |
                      (getYInRegYXXXX(Dd) << 22) |
                      (getXXXXInRegYXXXX(Dd) << 12) | Address;
   emitInst(Encoding);
 }
 
 void AssemblerARM32::vldrs(const Operand *OpSd, const Operand *OpAddress,
                            CondARM32::Cond Cond, const TargetInfo &TInfo) {
   // VDLR - ARM section A8.8.333, encoding A2.
   //   vldr<c> <Sd>, [<Rn>{, #+/-<imm>]]
   //
   // cccc1101UD01nnnndddd1010iiiiiiii where cccc=Cond, nnnn=Rn, ddddD=Sd,
   // iiiiiiii=abs(Opcode), and U=1 if Opcode >= 0;
   constexpr const char *Vldrs = "vldrs";
   IValueT Sd = encodeSRegister(OpSd, "Sd", Vldrs);
   assert(CondARM32::isDefined(Cond));
   IValueT Address;
   EncodedOperand AddressEncoding =
-      encodeAddress(OpAddress, Address, TInfo, ImmRegOffsetDiv4);
+      encodeAddress(OpAddress, Address, TInfo, RotatedImm8Div4Address);
   (void)AddressEncoding;
   assert(AddressEncoding == EncodedAsImmRegOffset);
   IValueT Encoding = B27 | B26 | B24 | B20 | B11 | B9 |
                      (encodeCondition(Cond) << kConditionShift) |
                      (getYInRegXXXXY(Sd) << 22) |
                      (getXXXXInRegXXXXY(Sd) << 12) | Address;
   emitInst(Encoding);
 }
 
 void AssemblerARM32::vmovsr(const Operand *OpSn, const Operand *OpRt,
@@ skipping 64 matching lines @@
   // VSTR - ARM section A8.8.413, encoding A1:
   //   vstr<c> <Dd>, [<Rn>{, #+/-<Imm>}]
   //
   // cccc1101UD00nnnndddd1011iiiiiiii where cccc=Cond, nnnn=Rn, Ddddd=Rd,
   // iiiiiiii=abs(Imm >> 2), and U=1 if Imm>=0.
   constexpr const char *Vstrd = "vstrd";
   IValueT Dd = encodeDRegister(OpDd, "Dd", Vstrd);
   assert(CondARM32::isDefined(Cond));
   IValueT Address;
   IValueT AddressEncoding =
-      encodeAddress(OpAddress, Address, TInfo, ImmRegOffsetDiv4);
+      encodeAddress(OpAddress, Address, TInfo, RotatedImm8Div4Address);
   (void)AddressEncoding;
   assert(AddressEncoding == EncodedAsImmRegOffset);
   IValueT Encoding = B27 | B26 | B24 | B11 | B9 | B8 |
                      (encodeCondition(Cond) << kConditionShift) |
                      (getYInRegYXXXX(Dd) << 22) |
                      (getXXXXInRegYXXXX(Dd) << 12) | Address;
   emitInst(Encoding);
 }
 
 void AssemblerARM32::vstrs(const Operand *OpSd, const Operand *OpAddress,
                            CondARM32::Cond Cond, const TargetInfo &TInfo) {
   // VSTR - ARM section A8.8.413, encoding A2:
   //   vstr<c> <Sd>, [<Rn>{, #+/-<imm>]]
   //
   // cccc1101UD01nnnndddd1010iiiiiiii where cccc=Cond, nnnn=Rn, ddddD=Sd,
   // iiiiiiii=abs(Opcode), and U=1 if Opcode >= 0;
   constexpr const char *Vstrs = "vstrs";
   IValueT Sd = encodeSRegister(OpSd, "Sd", Vstrs);
   assert(CondARM32::isDefined(Cond));
   IValueT Address;
   IValueT AddressEncoding =
-      encodeAddress(OpAddress, Address, TInfo, ImmRegOffsetDiv4);
+      encodeAddress(OpAddress, Address, TInfo, RotatedImm8Div4Address);
   (void)AddressEncoding;
   assert(AddressEncoding == EncodedAsImmRegOffset);
   IValueT Encoding =
       B27 | B26 | B24 | B11 | B9 | (encodeCondition(Cond) << kConditionShift) |
       (getYInRegXXXXY(Sd) << 22) | (getXXXXInRegXXXXY(Sd) << 12) | Address;
   emitInst(Encoding);
 }
 
 void AssemblerARM32::vsubs(const Operand *OpSd, const Operand *OpSn,
                            const Operand *OpSm, CondARM32::Cond Cond) {
@@ skipping 66 matching lines @@
   //
   // cccc11010D101101dddd1010iiiiiiii where cccc=Cond, ddddD=BaseReg, and
   // iiiiiiii=NumConsecRegs.
   constexpr IValueT VpushOpcode =
       B27 | B26 | B24 | B21 | B19 | B18 | B16 | B11 | B9;
   emitVStackOp(Cond, VpushOpcode, OpBaseReg, NumConsecRegs);
 }
 
 } // end of namespace ARM32
 } // end of namespace Ice