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Issue 1628133002: [turbofan] Add RoundUint32ToFloat32 operator to Turbofan. (Closed) Base URL: https://chromium.googlesource.com/v8/v8.git@master
Patch Set: add arm/arm64 implementation Created 4 years, 10 months ago
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1 // Copyright (c) 1994-2006 Sun Microsystems Inc. 1 // Copyright (c) 1994-2006 Sun Microsystems Inc.
2 // All Rights Reserved. 2 // All Rights Reserved.
3 // 3 //
4 // Redistribution and use in source and binary forms, with or without 4 // Redistribution and use in source and binary forms, with or without
5 // modification, are permitted provided that the following conditions 5 // modification, are permitted provided that the following conditions
6 // are met: 6 // are met:
7 // 7 //
8 // - Redistributions of source code must retain the above copyright notice, 8 // - Redistributions of source code must retain the above copyright notice,
9 // this list of conditions and the following disclaimer. 9 // this list of conditions and the following disclaimer.
10 // 10 //
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2916 2916
2917 2917
2918 void Assembler::vcvt_f64_u32(const DwVfpRegister dst, 2918 void Assembler::vcvt_f64_u32(const DwVfpRegister dst,
2919 const SwVfpRegister src, 2919 const SwVfpRegister src,
2920 VFPConversionMode mode, 2920 VFPConversionMode mode,
2921 const Condition cond) { 2921 const Condition cond) {
2922 emit(EncodeVCVT(F64, dst.code(), U32, src.code(), mode, cond)); 2922 emit(EncodeVCVT(F64, dst.code(), U32, src.code(), mode, cond));
2923 } 2923 }
2924 2924
2925 2925
2926 void Assembler::vcvt_f32_u32(const SwVfpRegister dst, const SwVfpRegister src,
2927 VFPConversionMode mode, const Condition cond) {
2928 emit(EncodeVCVT(F32, dst.code(), U32, src.code(), mode, cond));
2929 }
2930
2931
2926 void Assembler::vcvt_s32_f32(const SwVfpRegister dst, const SwVfpRegister src, 2932 void Assembler::vcvt_s32_f32(const SwVfpRegister dst, const SwVfpRegister src,
2927 VFPConversionMode mode, const Condition cond) { 2933 VFPConversionMode mode, const Condition cond) {
2928 emit(EncodeVCVT(S32, dst.code(), F32, src.code(), mode, cond)); 2934 emit(EncodeVCVT(S32, dst.code(), F32, src.code(), mode, cond));
2929 } 2935 }
2930 2936
2931 2937
2932 void Assembler::vcvt_s32_f64(const SwVfpRegister dst, 2938 void Assembler::vcvt_s32_f64(const SwVfpRegister dst,
2933 const DwVfpRegister src, 2939 const DwVfpRegister src,
2934 VFPConversionMode mode, 2940 VFPConversionMode mode,
2935 const Condition cond) { 2941 const Condition cond) {
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4111 DCHECK(is_uint12(offset)); 4117 DCHECK(is_uint12(offset));
4112 instr_at_put(pc, SetLdrRegisterImmediateOffset(instr, offset)); 4118 instr_at_put(pc, SetLdrRegisterImmediateOffset(instr, offset));
4113 } 4119 }
4114 } 4120 }
4115 4121
4116 4122
4117 } // namespace internal 4123 } // namespace internal
4118 } // namespace v8 4124 } // namespace v8
4119 4125
4120 #endif // V8_TARGET_ARCH_ARM 4126 #endif // V8_TARGET_ARCH_ARM
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