Implements intrinsics for MIPS.

runtime/vm/disassembler_mips.cc

 // Copyright (c) 2013, the Dart project authors.  Please see the AUTHORS file
 // for details. All rights reserved. Use of this source code is governed by a
 // BSD-style license that can be found in the LICENSE file.
 
 #include "vm/disassembler.h"
 
 #include "vm/globals.h"  // Needed here to get TARGET_ARCH_MIPS.
 #if defined(TARGET_ARCH_MIPS)
 #include "platform/assert.h"
 
@@ skipping 319 matching lines @@
       break;
     }
     case MOVN: {
       Format(instr, "movn 'rd, 'rs, 'rt");
       break;
     }
     case MOVZ: {
       Format(instr, "movz 'rd, 'rs, 'rt");
       break;
     }
+    case MTHI: {
+      Format(instr, "mthi 'rs");
+      break;
+    }
+    case MTLO: {
+      Format(instr, "mtlo 'rs");
+      break;
+    }
     case MULT: {
       Format(instr, "mult 'rs, 'rt");
       break;
     }
     case MULTU: {
       Format(instr, "multu 'rs, 'rt");
       break;
     }
     case NOR: {
       Format(instr, "nor 'rd, 'rs, 'rt");
@@ skipping 73 matching lines @@
       Unknown(instr);
       break;
     }
   }
 }
 
 
 void MIPSDecoder::DecodeSpecial2(Instr* instr) {
   ASSERT(instr->OpcodeField() == SPECIAL2);
   switch (instr->FunctionField()) {
+    case MADD: {
+      Format(instr, "madd 'rs, 'rt");
+      break;
+    }
+    case MADDU: {
+      Format(instr, "maddu 'rs, 'rt");
+      break;
+    }
     case CLO: {
       Format(instr, "clo 'rd, 'rs");
       break;
     }
     case CLZ: {
       Format(instr, "clz 'rd, 'rs");
       break;
     }
     default: {
       Unknown(instr);
@@ skipping 321 matching lines @@
                                   pc);
     pc += instruction_length;
   }
 
   return;
 }
 
 }  // namespace dart
 
 #endif  // defined TARGET_ARCH_MIPS