Add VMOV(immediate) instructions to the ARM assembler.

tests_lit/assembler/arm32/vmov-imm.ll

-; Test the "vmrs APSR_nzcv, FPSCR" form of the VMRS instruction.
+; Test moving constants into VPF registers.
 
 ; REQUIRES: allow_dump
 
 ; Compile using standalone assembler.
 ; RUN: %p2i --filetype=asm -i %s --target=arm32 --args -Om1 \
 ; RUN:   | FileCheck %s --check-prefix=ASM
 
 ; Show bytes in assembled standalone code.
 ; RUN: %p2i --filetype=asm -i %s --target=arm32 --assemble --disassemble \
 ; RUN:   --args -Om1 \
 ; RUN:   | FileCheck %s --check-prefix=DIS
 
 ; Compile using integrated assembler.
 ; RUN: %p2i --filetype=iasm -i %s --target=arm32 --args -Om1 \
 ; RUN:   | FileCheck %s --check-prefix=IASM
 
 ; Show bytes in assembled integrated code.
 ; RUN: %p2i --filetype=iasm -i %s --target=arm32 --assemble --disassemble \
 ; RUN:   --args -Om1 \
 ; RUN:   | FileCheck %s --check-prefix=DIS
 
-define internal i32 @testVmrsASPR_nzcv() {
-; ASM-LABEL: testVmrsASPR_nzcv:
-; DIS-LABEL: 00000000 <testVmrsASPR_nzcv>:
+define internal void @testMoveDouble() {
+; ASM-LABEL: testMoveDouble:
+; DIS-LABEL: 00000000 <testMoveDouble>:
 
 entry:
-; ASM: .LtestVmrsASPR_nzcv$entry:
+  %addr = inttoptr i32 0 to double*
+  store double 0.5, double* %addr, align 8
 
-  %test = fcmp olt float 0.0, 0.0
+; ASM:  vmov.f64        d0, #5.000000e-01
+; DIS:    4:    eeb60b00
+; IASM-NOT: vmov.f64
 
-; ASM:  vmrs    APSR_nzcv, FPSCR
-; DIS:   14:    eef1fa10
-; IASM-NOT: vmrs
+  ret void
+}
 
-  %result = zext i1 %test to i32
-  ret i32 %result
+define internal void @testMoveFloat() {
+; ASM-LABEL: testMoveFloat:
+; DIS-LABEL: 00000010 <testMoveFloat>:
+
+entry:
+  %addr = inttoptr i32 0 to float*
+  store float 0.5, float* %addr, align 4
+
+; ASM:  vmov.f32        s0, #5.000000e-01
+; DIS:   14:    eeb60a00
+; IASM-NOT: vmov.f32
+
+  ret void
 }