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| 1 // Copyright (c) 2013, the Dart project authors. Please see the AUTHORS file | 1 // Copyright (c) 2013, the Dart project authors. Please see the AUTHORS file |
| 2 // for details. All rights reserved. Use of this source code is governed by a | 2 // for details. All rights reserved. Use of this source code is governed by a |
| 3 // BSD-style license that can be found in the LICENSE file. | 3 // BSD-style license that can be found in the LICENSE file. |
| 4 // | 4 // |
| 5 // This is forked from Dart revision df52deea9f25690eb8b66c5995da92b70f7ac1fe | 5 // This is forked from Dart revision df52deea9f25690eb8b66c5995da92b70f7ac1fe |
| 6 // Please update the (git) revision if we merge changes from Dart. | 6 // Please update the (git) revision if we merge changes from Dart. |
| 7 // https://code.google.com/p/dart/wiki/GettingTheSource | 7 // https://code.google.com/p/dart/wiki/GettingTheSource |
| 8 | 8 |
| 9 #include "vm/globals.h" // NOLINT | 9 #include "vm/globals.h" // NOLINT |
| 10 #if defined(TARGET_ARCH_ARM) | 10 #if defined(TARGET_ARCH_ARM) |
| (...skipping 1104 matching lines...) Expand 10 before | Expand all | Expand 10 after Loading... |
| 1115 // Moved to ARM32::AssemblerARM32::vcvtis() | 1115 // Moved to ARM32::AssemblerARM32::vcvtis() |
| 1116 void Assembler::vcvtis(SRegister sd, SRegister sm, Condition cond) { | 1116 void Assembler::vcvtis(SRegister sd, SRegister sm, Condition cond) { |
| 1117 EmitVFPsss(cond, B23 | B21 | B20 | B19 | B18 | B16 | B7 | B6, sd, S0, sm); | 1117 EmitVFPsss(cond, B23 | B21 | B20 | B19 | B18 | B16 | B7 | B6, sd, S0, sm); |
| 1118 } | 1118 } |
| 1119 #endif | 1119 #endif |
| 1120 | 1120 |
| 1121 void Assembler::vcvtid(SRegister sd, DRegister dm, Condition cond) { | 1121 void Assembler::vcvtid(SRegister sd, DRegister dm, Condition cond) { |
| 1122 EmitVFPsd(cond, B23 | B21 | B20 | B19 | B18 | B16 | B8 | B7 | B6, sd, dm); | 1122 EmitVFPsd(cond, B23 | B21 | B20 | B19 | B18 | B16 | B8 | B7 | B6, sd, dm); |
| 1123 } | 1123 } |
| 1124 | 1124 |
| 1125 | 1125 #if 0 |
| 1126 // Moved to ARM32::AssemblerARM32::vcvtsi() |
| 1126 void Assembler::vcvtsi(SRegister sd, SRegister sm, Condition cond) { | 1127 void Assembler::vcvtsi(SRegister sd, SRegister sm, Condition cond) { |
| 1127 EmitVFPsss(cond, B23 | B21 | B20 | B19 | B7 | B6, sd, S0, sm); | 1128 EmitVFPsss(cond, B23 | B21 | B20 | B19 | B7 | B6, sd, S0, sm); |
| 1128 } | 1129 } |
| 1129 | 1130 |
| 1130 | 1131 // Moved to ARM32::AssemblerARM32::vcvtdi() |
| 1131 void Assembler::vcvtdi(DRegister dd, SRegister sm, Condition cond) { | 1132 void Assembler::vcvtdi(DRegister dd, SRegister sm, Condition cond) { |
| 1132 EmitVFPds(cond, B23 | B21 | B20 | B19 | B8 | B7 | B6, dd, sm); | 1133 EmitVFPds(cond, B23 | B21 | B20 | B19 | B8 | B7 | B6, dd, sm); |
| 1133 } | 1134 } |
| 1134 | 1135 |
| 1135 | 1136 // Moved to ARM32::AssemblerARM32::vcvtus(). |
| 1136 void Assembler::vcvtus(SRegister sd, SRegister sm, Condition cond) { | 1137 void Assembler::vcvtus(SRegister sd, SRegister sm, Condition cond) { |
| 1137 EmitVFPsss(cond, B23 | B21 | B20 | B19 | B18 | B7 | B6, sd, S0, sm); | 1138 EmitVFPsss(cond, B23 | B21 | B20 | B19 | B18 | B7 | B6, sd, S0, sm); |
| 1138 } | 1139 } |
| 1139 | 1140 |
| 1140 | 1141 // Moved to ARM32::AssemblerARM32::vcvtud(). |
| 1141 void Assembler::vcvtud(SRegister sd, DRegister dm, Condition cond) { | 1142 void Assembler::vcvtud(SRegister sd, DRegister dm, Condition cond) { |
| 1142 EmitVFPsd(cond, B23 | B21 | B20 | B19 | B18 | B8 | B7 | B6, sd, dm); | 1143 EmitVFPsd(cond, B23 | B21 | B20 | B19 | B18 | B8 | B7 | B6, sd, dm); |
| 1143 } | 1144 } |
| 1144 | 1145 |
| 1145 | 1146 // Moved to ARM32::AssemblerARM32::vcvtsu() |
| 1146 void Assembler::vcvtsu(SRegister sd, SRegister sm, Condition cond) { | 1147 void Assembler::vcvtsu(SRegister sd, SRegister sm, Condition cond) { |
| 1147 EmitVFPsss(cond, B23 | B21 | B20 | B19 | B6, sd, S0, sm); | 1148 EmitVFPsss(cond, B23 | B21 | B20 | B19 | B6, sd, S0, sm); |
| 1148 } | 1149 } |
| 1149 | 1150 |
| 1150 | 1151 // Moved to ARM32::AssemblerARM32::vcvtdu() |
| 1151 void Assembler::vcvtdu(DRegister dd, SRegister sm, Condition cond) { | 1152 void Assembler::vcvtdu(DRegister dd, SRegister sm, Condition cond) { |
| 1152 EmitVFPds(cond, B23 | B21 | B20 | B19 | B8 | B6, dd, sm); | 1153 EmitVFPds(cond, B23 | B21 | B20 | B19 | B8 | B6, dd, sm); |
| 1153 } | 1154 } |
| 1154 | 1155 |
| 1155 #if 0 | |
| 1156 // Moved to ARM23::AssemblerARM32::vcmps(). | 1156 // Moved to ARM23::AssemblerARM32::vcmps(). |
| 1157 void Assembler::vcmps(SRegister sd, SRegister sm, Condition cond) { | 1157 void Assembler::vcmps(SRegister sd, SRegister sm, Condition cond) { |
| 1158 EmitVFPsss(cond, B23 | B21 | B20 | B18 | B6, sd, S0, sm); | 1158 EmitVFPsss(cond, B23 | B21 | B20 | B18 | B6, sd, S0, sm); |
| 1159 } | 1159 } |
| 1160 | 1160 |
| 1161 // Moved to ARM23::AssemblerARM32::vcmpd(). | 1161 // Moved to ARM23::AssemblerARM32::vcmpd(). |
| 1162 void Assembler::vcmpd(DRegister dd, DRegister dm, Condition cond) { | 1162 void Assembler::vcmpd(DRegister dd, DRegister dm, Condition cond) { |
| 1163 EmitVFPddd(cond, B23 | B21 | B20 | B18 | B6, dd, D0, dm); | 1163 EmitVFPddd(cond, B23 | B21 | B20 | B18 | B6, dd, D0, dm); |
| 1164 } | 1164 } |
| 1165 | 1165 |
| (...skipping 2523 matching lines...) Expand 10 before | Expand all | Expand 10 after Loading... |
| 3689 | 3689 |
| 3690 | 3690 |
| 3691 const char* Assembler::FpuRegisterName(FpuRegister reg) { | 3691 const char* Assembler::FpuRegisterName(FpuRegister reg) { |
| 3692 ASSERT((0 <= reg) && (reg < kNumberOfFpuRegisters)); | 3692 ASSERT((0 <= reg) && (reg < kNumberOfFpuRegisters)); |
| 3693 return fpu_reg_names[reg]; | 3693 return fpu_reg_names[reg]; |
| 3694 } | 3694 } |
| 3695 | 3695 |
| 3696 } // namespace dart | 3696 } // namespace dart |
| 3697 | 3697 |
| 3698 #endif // defined TARGET_ARCH_ARM | 3698 #endif // defined TARGET_ARCH_ARM |
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