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Issue 16206004: Add smi support to all binops minus shr, sar, shl, div and mod. (Closed) Base URL: https://v8.googlecode.com/svn/branches/bleeding_edge
Patch Set: Created 7 years, 6 months ago
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1 // Copyright 2011 the V8 project authors. All rights reserved. 1 // Copyright 2011 the V8 project authors. All rights reserved.
2 // Redistribution and use in source and binary forms, with or without 2 // Redistribution and use in source and binary forms, with or without
3 // modification, are permitted provided that the following conditions are 3 // modification, are permitted provided that the following conditions are
4 // met: 4 // met:
5 // 5 //
6 // * Redistributions of source code must retain the above copyright 6 // * Redistributions of source code must retain the above copyright
7 // notice, this list of conditions and the following disclaimer. 7 // notice, this list of conditions and the following disclaimer.
8 // * Redistributions in binary form must reproduce the above 8 // * Redistributions in binary form must reproduce the above
9 // copyright notice, this list of conditions and the following 9 // copyright notice, this list of conditions and the following
10 // disclaimer in the documentation and/or other materials provided 10 // disclaimer in the documentation and/or other materials provided
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299 Register tmp = EnsureTempRegister(); 299 Register tmp = EnsureTempRegister();
300 Operand dst = cgen_->ToOperand(destination); 300 Operand dst = cgen_->ToOperand(destination);
301 __ mov(tmp, src); 301 __ mov(tmp, src);
302 __ mov(dst, tmp); 302 __ mov(dst, tmp);
303 } 303 }
304 304
305 } else if (source->IsConstantOperand()) { 305 } else if (source->IsConstantOperand()) {
306 LConstantOperand* constant_source = LConstantOperand::cast(source); 306 LConstantOperand* constant_source = LConstantOperand::cast(source);
307 if (destination->IsRegister()) { 307 if (destination->IsRegister()) {
308 Register dst = cgen_->ToRegister(destination); 308 Register dst = cgen_->ToRegister(destination);
309 if (cgen_->IsSmi(constant_source)) { 309 Representation r = cgen_->IsSmi(constant_source)
310 __ Set(dst, cgen_->ToSmiImmediate(constant_source)); 310 ? Representation::Smi() : Representation::Integer32();
311 } else if (cgen_->IsInteger32(constant_source)) { 311 if (cgen_->IsInteger32(constant_source)) {
312 __ Set(dst, cgen_->ToInteger32Immediate(constant_source)); 312 __ Set(dst, cgen_->ToImmediate(constant_source, r));
313 } else { 313 } else {
314 __ LoadObject(dst, cgen_->ToHandle(constant_source)); 314 __ LoadObject(dst, cgen_->ToHandle(constant_source));
315 } 315 }
316 } else { 316 } else {
317 ASSERT(destination->IsStackSlot()); 317 ASSERT(destination->IsStackSlot());
318 Operand dst = cgen_->ToOperand(destination); 318 Operand dst = cgen_->ToOperand(destination);
319 if (cgen_->IsSmi(constant_source)) { 319 Representation r = cgen_->IsSmi(constant_source)
320 __ Set(dst, cgen_->ToSmiImmediate(constant_source)); 320 ? Representation::Smi() : Representation::Integer32();
321 } else if (cgen_->IsInteger32(constant_source)) { 321 if (cgen_->IsInteger32(constant_source)) {
322 __ Set(dst, cgen_->ToInteger32Immediate(constant_source)); 322 __ Set(dst, cgen_->ToImmediate(constant_source, r));
323 } else { 323 } else {
324 Register tmp = EnsureTempRegister(); 324 Register tmp = EnsureTempRegister();
325 __ LoadObject(tmp, cgen_->ToHandle(constant_source)); 325 __ LoadObject(tmp, cgen_->ToHandle(constant_source));
326 __ mov(dst, tmp); 326 __ mov(dst, tmp);
327 } 327 }
328 } 328 }
329 329
330 } else if (source->IsDoubleRegister()) { 330 } else if (source->IsDoubleRegister()) {
331 if (CpuFeatures::IsSupported(SSE2)) { 331 if (CpuFeatures::IsSupported(SSE2)) {
332 CpuFeatureScope scope(cgen_->masm(), SSE2); 332 CpuFeatureScope scope(cgen_->masm(), SSE2);
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519 } else if (destination->IsRegister()) { 519 } else if (destination->IsRegister()) {
520 source_uses_[destination->index()] = CountSourceUses(destination); 520 source_uses_[destination->index()] = CountSourceUses(destination);
521 } 521 }
522 } 522 }
523 523
524 #undef __ 524 #undef __
525 525
526 } } // namespace v8::internal 526 } } // namespace v8::internal
527 527
528 #endif // V8_TARGET_ARCH_IA32 528 #endif // V8_TARGET_ARCH_IA32
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