Fix vldrd/vstrd handling of immediate offsets in ARM.

tests_lit/assembler/arm32/vldr.vstr.imm.ll

Index: tests_lit/assembler/arm32/vldr.vstr.imm.ll
diff --git a/tests_lit/assembler/arm32/veor.ll b/tests_lit/assembler/arm32/vldr.vstr.imm.ll
similarity index 55%
copy from tests_lit/assembler/arm32/veor.ll
copy to tests_lit/assembler/arm32/vldr.vstr.imm.ll
index 8b138a1760b417ec33bdd49500e25fb9dd3618bc..0fa12b00cddd954b380a6d752d90495e588f12c8 100644
--- a/tests_lit/assembler/arm32/veor.ll
+++ b/tests_lit/assembler/arm32/vldr.vstr.imm.ll
@@ -1,37 +1,47 @@
-; Show that we know how to translate veor. Does this by noting that
-; loading a double 0.0 introduces a veor.
+; Test vldrd and vstrd when address is offset with an immediate.
 
 ; REQUIRES: allow_dump
 
 ; Compile using standalone assembler.
 ; RUN: %p2i --filetype=asm -i %s --target=arm32 --args -Om1 \
+; RUN:   -reg-use d20 \
 ; RUN:   | FileCheck %s --check-prefix=ASM
 
 ; Show bytes in assembled standalone code.
 ; RUN: %p2i --filetype=asm -i %s --target=arm32 --assemble --disassemble \
 ; RUN:   --args -Om1 \
+; RUN:   -reg-use d20 \
 ; RUN:   | FileCheck %s --check-prefix=DIS
 
 ; Compile using integrated assembler.
 ; RUN: %p2i --filetype=iasm -i %s --target=arm32 --args -Om1 \
+; RUN:   -reg-use d20 \
 ; RUN:   | FileCheck %s --check-prefix=IASM
 
 ; Show bytes in assembled integrated code.
 ; RUN: %p2i --filetype=iasm -i %s --target=arm32 --assemble --disassemble \
 ; RUN:   --args -Om1 \
+; RUN:   -reg-use d20 \
 ; RUN:   | FileCheck %s --check-prefix=DIS
 
-define internal double @testVeor() {
-; ASM-LABEL: testVeor:
-; DIS: 00000000 <testVeor>:
+define internal i64 @testVldrStrImm(double %d) {
+; ASM-LABEL: testVldrStrImm:
+; DIS-LABEL: 00000000 <testVldrStrImm>:
+; IASM-LABEL: testVldrStrImm:
 
 entry:
-; ASM: .LtestVeor$entry:
+; ASM-NEXT: .LtestVldrStrImm$entry:
+; IASM-NEXT: .LtestVldrStrImm$entry:
 
-  ret double 0.0
+; ASM:  vstr    d0, [sp, #8]
+; DIS:    4:   ed8d0b02
+; IASM-NOT: vstr
 
-; ASM:  veor.f64        d0, d0, d0
-; DIS:    0:    f3000110
-; IASM-NOT: veor
+  %v = bitcast double %d to i64
 
+; ASM:  vldr    d20, [sp, #8]
+; DIS:    8:   eddd4b02
+; IASM-NOT: vldr
+
+  ret i64 %v
 }