Fix vldrd/vstrd handling of immediate offsets in ARM.

src/IceAssemblerARM32.cpp

 //===- subzero/src/IceAssemblerARM32.cpp - Assembler for ARM32 --*- C++ -*-===//
 //
 // Copyright (c) 2013, the Dart project authors.  Please see the AUTHORS file
 // for details. All rights reserved. Use of this source code is governed by a
 // BSD-style license that can be found in the LICENSE file.
 //
 // Modified by the Subzero authors.
 //
 //===----------------------------------------------------------------------===//
 //
@@ skipping 162 matching lines @@
 // Returns the GPR register at given Shift in Value.
 RegARM32::GPRRegister getGPRReg(IValueT Shift, IValueT Value) {
   return decodeGPRRegister((Value >> Shift) & 0xF);
 }
 
 // Defines alternate layouts of instruction operands, should the (common)
 // default pattern not be used.
 enum OpEncoding {
   // No alternate layout specified.
   DefaultOpEncoding,
+  // Alternate encoding for ImmRegOffset, where the offset is divided by 4
+  // before encoding.
+  ImmRegOffsetDiv4,
   // Alternate encoding 3 for memory operands (like in strb, strh, ldrb, and
   // ldrh.
   OpEncoding3,
   // Alternate encoding for memory operands for ldrex and strex, which only
   // actually expect a register.
   OpEncodingMemEx
 };
 
 IValueT getEncodedGPRegNum(const Variable *Var) {
   assert(Var->hasReg());
@@ skipping 181 matching lines @@
   assert(Imm8 < (1 << 8));
   Value = Value | B22 | ((Imm8 & 0xf0) << 4) | (Imm8 & 0x0f);
   return Value;
 }
 
 IValueT encodeImmRegOffset(OpEncoding AddressEncoding, IValueT Reg,
                            IOffsetT Offset, OperandARM32Mem::AddrMode Mode) {
   switch (AddressEncoding) {
   case DefaultOpEncoding:
     return encodeImmRegOffset(Reg, Offset, Mode);
+  case ImmRegOffsetDiv4:
+    assert((Offset & 0x3) == 0);
+    return encodeImmRegOffset(Reg, Offset >> 2, Mode);
   case OpEncoding3:
     return encodeImmRegOffsetEnc3(Reg, Offset, Mode);
   case OpEncodingMemEx:
     assert(Offset == 0);
     assert(Mode == OperandARM32Mem::Offset);
     return Reg << kRnShift;
   }
   llvm_unreachable("(silence g++ warning)");
 }
 
@@ skipping 1813 matching lines @@
       (getYInRegYXXXX(Dm) << 5) | getXXXXInRegYXXXX(Dm);
   emitInst(Encoding);
 }
 
 void AssemblerARM32::vldrd(const Operand *OpDd, const Operand *OpAddress,
                            CondARM32::Cond Cond, const TargetInfo &TInfo) {
   // VLDR - ARM section A8.8.333, encoding A1.
   //   vldr<c> <Dd>, [<Rn>{, #+/-<imm>}]
   //
   // cccc1101UD01nnnndddd1011iiiiiiii where cccc=Cond, nnnn=Rn, Ddddd=Rd,
-  // iiiiiiii=abs(Opcode), and U=1 if Opcode>=0,
+  // iiiiiiii=abs(Imm >> 2), and U=1 if Opcode>=0.
   constexpr const char *Vldrd = "vldrd";
   IValueT Dd = encodeDRegister(OpDd, "Dd", Vldrd);
   assert(CondARM32::isDefined(Cond));
   IValueT Address;
-  EncodedOperand AddressEncoding = encodeAddress(OpAddress, Address, TInfo);
-  (void)AddressEncoding;
-  assert(AddressEncoding == EncodedAsImmRegOffset);
+  EncodedOperand AddressEncoding =
+      encodeAddress(OpAddress, Address, TInfo, ImmRegOffsetDiv4);
+  if (AddressEncoding != EncodedAsImmRegOffset)
+    // TODO(kschimpf) Fix this.
+    return setNeedsTextFixup();
   AssemblerBuffer::EnsureCapacity ensured(&Buffer);
   IValueT Encoding = B27 | B26 | B24 | B20 | B11 | B9 | B8 |
                      (encodeCondition(Cond) << kConditionShift) |
                      (getYInRegYXXXX(Dd) << 22) |
                      (getXXXXInRegYXXXX(Dd) << 12) | Address;
   emitInst(Encoding);
 }
 
 void AssemblerARM32::vldrs(const Operand *OpSd, const Operand *OpAddress,
                            CondARM32::Cond Cond, const TargetInfo &TInfo) {
@@ skipping 43 matching lines @@
   IValueT Dd = encodeDRegister(OpDd, "Dd", Vmuld);
   IValueT Dn = encodeDRegister(OpDn, "Dn", Vmuld);
   IValueT Dm = encodeDRegister(OpDm, "Dm", Vmuld);
   constexpr IValueT VmuldOpcode = B21;
   emitVFPddd(Cond, VmuldOpcode, Dd, Dn, Dm);
 }
 
 void AssemblerARM32::vstrd(const Operand *OpDd, const Operand *OpAddress,
                            CondARM32::Cond Cond, const TargetInfo &TInfo) {
   // VSTR - ARM section A8.8.413, encoding A1:
-  //   vstr<c> <Dd>, [<Rn>{, #+/-<imm>}]
+  //   vstr<c> <Dd>, [<Rn>{, #+/-<Imm>}]
   //
   // cccc1101UD00nnnndddd1011iiiiiiii where cccc=Cond, nnnn=Rn, Ddddd=Rd,
-  // iiiiiiii=abs(Opcode), and U=1 if Opcode>=0,
+  // iiiiiiii=abs(Imm >> 2), and U=1 if Imm>=0.
   constexpr const char *Vstrd = "vstrd";
   IValueT Dd = encodeDRegister(OpDd, "Dd", Vstrd);
   assert(CondARM32::isDefined(Cond));
   IValueT Address;
-  if (encodeAddress(OpAddress, Address, TInfo) != EncodedAsImmRegOffset)
-    assert(false);
+  IValueT AddressEncoding =
+      encodeAddress(OpAddress, Address, TInfo, ImmRegOffsetDiv4);
+  if (AddressEncoding != EncodedAsImmRegOffset)
+    // TODO(kschimpf) Fix this.
+    return setNeedsTextFixup();
   AssemblerBuffer::EnsureCapacity ensured(&Buffer);
   IValueT Encoding = B27 | B26 | B24 | B11 | B9 | B8 |
                      (encodeCondition(Cond) << kConditionShift) |
                      (getYInRegYXXXX(Dd) << 22) |
                      (getXXXXInRegYXXXX(Dd) << 12) | Address;
   emitInst(Encoding);
 }
 
 void AssemblerARM32::vstrs(const Operand *OpSd, const Operand *OpAddress,
                            CondARM32::Cond Cond, const TargetInfo &TInfo) {
@@ skipping 87 matching lines @@
   //
   // cccc11010D101101dddd1010iiiiiiii where cccc=Cond, ddddD=BaseReg, and
   // iiiiiiii=NumConsecRegs.
   constexpr IValueT VpushOpcode =
       B27 | B26 | B24 | B21 | B19 | B18 | B16 | B11 | B9;
   emitVStackOp(Cond, VpushOpcode, OpBaseReg, NumConsecRegs);
 }
 
 } // end of namespace ARM32
 } // end of namespace Ice