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| 1 // Copyright (c) 2013, the Dart project authors. Please see the AUTHORS file | 1 // Copyright (c) 2013, the Dart project authors. Please see the AUTHORS file |
| 2 // for details. All rights reserved. Use of this source code is governed by a | 2 // for details. All rights reserved. Use of this source code is governed by a |
| 3 // BSD-style license that can be found in the LICENSE file. | 3 // BSD-style license that can be found in the LICENSE file. |
| 4 | 4 |
| 5 #include "vm/globals.h" | 5 #include "vm/globals.h" |
| 6 #if defined(TARGET_ARCH_ARM) | 6 #if defined(TARGET_ARCH_ARM) |
| 7 | 7 |
| 8 #include "vm/assembler.h" | 8 #include "vm/assembler.h" |
| 9 #include "vm/os.h" | 9 #include "vm/os.h" |
| 10 #include "vm/unit_test.h" | 10 #include "vm/unit_test.h" |
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| 1411 } | 1411 } |
| 1412 | 1412 |
| 1413 | 1413 |
| 1414 ASSEMBLER_TEST_RUN(VstmsVldms_off, test) { | 1414 ASSEMBLER_TEST_RUN(VstmsVldms_off, test) { |
| 1415 EXPECT(test != NULL); | 1415 EXPECT(test != NULL); |
| 1416 typedef int (*Tst)(); | 1416 typedef int (*Tst)(); |
| 1417 EXPECT_EQ(42, EXECUTE_TEST_CODE_INT32(Tst, test->entry())); | 1417 EXPECT_EQ(42, EXECUTE_TEST_CODE_INT32(Tst, test->entry())); |
| 1418 } | 1418 } |
| 1419 | 1419 |
| 1420 | 1420 |
| 1421 // Check that assembler mrc instruction encoding, and simulator decoding | |
| 1422 // are in agreement. | |
| 1423 #if defined(USING_SIMULATOR) | |
| 1424 ASSEMBLER_TEST_GENERATE(MrcHaveDiv, assembler) { | |
| 1425 __ mrc(R0, 15, 0, 0, 2, 0); // Accesses ID_ISAR0. | |
| 1426 // Bits 24 - 27 describe the presence of integer division. Bit 24 is set if | |
| 1427 // it is available in the Thumb instruction set. Bit 25 is set if it is | |
| 1428 // available both in Thumb and in the ARM instruction set. | |
| 1429 __ Lsr(R0, R0, 24); | |
| 1430 __ and_(R0, R0, ShifterOperand(0xf)); | |
| 1431 __ bx(LR); | |
| 1432 } | |
| 1433 | |
| 1434 | |
| 1435 ASSEMBLER_TEST_RUN(MrcHaveDiv, test) { | |
| 1436 EXPECT(test != NULL); | |
| 1437 typedef int (*Tst)(); | |
| 1438 bool b = CPUFeatures::integer_division_supported(); | |
| 1439 CPUFeatures::set_integer_division_supported(true); | |
| 1440 EXPECT_EQ(2, EXECUTE_TEST_CODE_INT32(Tst, test->entry())); | |
| 1441 CPUFeatures::set_integer_division_supported(b); | |
| 1442 } | |
| 1443 | |
| 1444 | |
| 1445 ASSEMBLER_TEST_GENERATE(MrcNoDiv, assembler) { | |
| 1446 __ mrc(R0, 15, 0, 0, 2, 0); | |
| 1447 __ Lsr(R0, R0, 24); | |
| 1448 __ and_(R0, R0, ShifterOperand(0xf)); | |
| 1449 __ bx(LR); | |
| 1450 } | |
| 1451 | |
| 1452 | |
| 1453 ASSEMBLER_TEST_RUN(MrcNoDiv, test) { | |
| 1454 EXPECT(test != NULL); | |
| 1455 typedef int (*Tst)(); | |
| 1456 bool b = CPUFeatures::integer_division_supported(); | |
| 1457 CPUFeatures::set_integer_division_supported(false); | |
| 1458 EXPECT_EQ(0, EXECUTE_TEST_CODE_INT32(Tst, test->entry())); | |
| 1459 CPUFeatures::set_integer_division_supported(b); | |
| 1460 } | |
| 1461 | |
| 1462 | |
| 1463 ASSEMBLER_TEST_GENERATE(MrcReal, assembler) { | |
| 1464 __ mrc(R0, 15, 0, 0, 2, 0); | |
| 1465 __ Lsr(R0, R0, 24); | |
| 1466 __ and_(R0, R0, ShifterOperand(0xf)); | |
| 1467 __ bx(LR); | |
| 1468 } | |
| 1469 | |
| 1470 | |
| 1471 ASSEMBLER_TEST_RUN(MrcReal, test) { | |
| 1472 EXPECT(test != NULL); | |
| 1473 typedef int (*Tst)(); | |
| 1474 bool have_div = CPUFeatures::integer_division_supported(); | |
| 1475 int32_t r = EXECUTE_TEST_CODE_INT32(Tst, test->entry()); | |
| 1476 if (have_div) { | |
| 1477 EXPECT_EQ(2, r); | |
| 1478 } else { | |
| 1479 EXPECT_EQ(0, r); | |
| 1480 } | |
| 1481 } | |
| 1482 #endif // defined(USING_SIMULATOR) | |
| 1483 | |
| 1484 | |
| 1485 ASSEMBLER_TEST_GENERATE(Udiv, assembler) { | 1421 ASSEMBLER_TEST_GENERATE(Udiv, assembler) { |
| 1486 if (CPUFeatures::integer_division_supported()) { | 1422 if (CPUFeatures::integer_division_supported()) { |
| 1487 __ mov(R0, ShifterOperand(27)); | 1423 __ mov(R0, ShifterOperand(27)); |
| 1488 __ mov(R1, ShifterOperand(9)); | 1424 __ mov(R1, ShifterOperand(9)); |
| 1489 __ udiv(R2, R0, R1); | 1425 __ udiv(R2, R0, R1); |
| 1490 __ Mov(R0, R2); | 1426 __ Mov(R0, R2); |
| 1491 } else { | 1427 } else { |
| 1492 __ mov(R0, ShifterOperand(3)); | 1428 __ mov(R0, ShifterOperand(3)); |
| 1493 } | 1429 } |
| 1494 __ bx(LR); | 1430 __ bx(LR); |
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| 1630 __ StoreIntoObject(R2, | 1566 __ StoreIntoObject(R2, |
| 1631 FieldAddress(R2, GrowableObjectArray::data_offset()), | 1567 FieldAddress(R2, GrowableObjectArray::data_offset()), |
| 1632 R1); | 1568 R1); |
| 1633 __ PopList((1 << CTX) | (1 << LR)); | 1569 __ PopList((1 << CTX) | (1 << LR)); |
| 1634 __ Ret(); | 1570 __ Ret(); |
| 1635 } | 1571 } |
| 1636 | 1572 |
| 1637 } // namespace dart | 1573 } // namespace dart |
| 1638 | 1574 |
| 1639 #endif // defined TARGET_ARCH_ARM | 1575 #endif // defined TARGET_ARCH_ARM |
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