Merged addProlog and addEpilog on x86.

src/IceTargetLoweringX86Base.h

 //===- subzero/src/IceTargetLoweringX86Base.h - x86 lowering ----*- C++ -*-===//
 //
 //                        The Subzero Code Generator
 //
 // This file is distributed under the University of Illinois Open Source
 // License. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
 ///
 /// \file
@@ skipping 159 matching lines @@
 
   template <typename T = Traits>
   typename std::enable_if<!T::Is64Bit, Operand>::type *
   hiOperand(Operand *Operand);
   template <typename T = Traits>
   typename std::enable_if<T::Is64Bit, Operand>::type *hiOperand(Operand *) {
     llvm::report_fatal_error(
         "Hey, yo! This is x86-64. Watcha doin'? (hiOperand)");
   }
 
+  void addProlog(CfgNode *Node) override;
   void finishArgumentLowering(Variable *Arg, Variable *FramePtr,
                               size_t BasicFrameOffset, size_t StackAdjBytes,
                               size_t &InArgsSizeBytes);
+  void addEpilog(CfgNode *Node) override;
   X86Address stackVarToAsmOperand(const Variable *Var) const;
 
   InstructionSetEnum getInstructionSet() const { return InstructionSet; }
   Operand *legalizeUndef(Operand *From, int32_t RegNum = Variable::NoRegister);
 
 protected:
   const bool NeedSandboxing;
 
   explicit TargetX86Base(Cfg *Func);
 
@@ skipping 82 matching lines @@
 
   using LowerBinOp = void (TargetX86Base::*)(Variable *, Operand *);
   void expandAtomicRMWAsCmpxchg(LowerBinOp op_lo, LowerBinOp op_hi,
                                 Variable *Dest, Operand *Ptr, Operand *Val);
 
   void eliminateNextVectorSextInstruction(Variable *SignExtendedResult);
 
   void scalarizeArithmetic(InstArithmetic::OpKind K, Variable *Dest,
                            Operand *Src0, Operand *Src1);
 
+  void emitGetIP(CfgNode *Node) {
+    dispatchToConcrete(&Traits::ConcreteTarget::emitGetIP, std::move(Node));
+  }
+  /// Emit a sandboxed return sequence rather than a return.
+  virtual void emitSandboxedReturn() {

[John, 2016/01/21 15:04:52]

is virtual needed here?

[sehr, 2016/01/21 16:02:10]

Removed.

+    dispatchToConcrete(&Traits::ConcreteTarget::emitSandboxedReturn);
+  }
   /// Emit just the call instruction (without argument or return variable
   /// processing), sandboxing if needed.
   virtual Inst *emitCallToTarget(Operand *CallTarget, Variable *ReturnReg) = 0;
   /// Materialize the moves needed to return a value of the specified type.
   virtual Variable *moveReturnValueToRegister(Operand *Value,
                                               Type ReturnType) = 0;
 
   /// Emit a fake use of esp to make sure esp stays alive for the entire
   /// function. Otherwise some esp adjustments get dead-code eliminated.
   void keepEspLiveAtExit() {
@@ skipping 286 matching lines @@
     AutoMemorySandboxer<> _(this, &Dest, &Src0, &Src1);
     Context.insert<typename Traits::Insts::Insertps>(Dest, Src0, Src1);
   }
   void _jmp(Operand *Target) {
     AutoMemorySandboxer<> _(this, &Target);
     Context.insert<typename Traits::Insts::Jmp>(Target);
   }
   void _lea(Variable *Dest, Operand *Src0) {
     Context.insert<typename Traits::Insts::Lea>(Dest, Src0);
   }
+  void _link_bp() { dispatchToConcrete(&Traits::ConcreteTarget::_link_bp); }
+  void _push_reg(Variable *Reg) {
+    dispatchToConcrete(&Traits::ConcreteTarget::_push_reg, std::move(Reg));
+  }
   void _mfence() { Context.insert<typename Traits::Insts::Mfence>(); }
   /// Moves can be used to redefine registers, creating "partial kills" for
   /// liveness.  Mark where moves are used in this way.
   void _redefined(Inst *MovInst, bool IsRedefinition = true) {
     if (IsRedefinition)
       MovInst->setDestRedefined();
   }
   /// If Dest=nullptr is passed in, then a new variable is created, marked as
   /// infinite register allocation weight, and returned through the in/out Dest
   /// argument.
@@ skipping 228 matching lines @@
   }
   void _test(Operand *Src0, Operand *Src1) {
     AutoMemorySandboxer<> _(this, &Src0, &Src1);
     Context.insert<typename Traits::Insts::Test>(Src0, Src1);
   }
   void _ucomiss(Operand *Src0, Operand *Src1) {
     AutoMemorySandboxer<> _(this, &Src0, &Src1);
     Context.insert<typename Traits::Insts::Ucomiss>(Src0, Src1);
   }
   void _ud2() { Context.insert<typename Traits::Insts::UD2>(); }
+  void _unlink_bp() { dispatchToConcrete(&Traits::ConcreteTarget::_unlink_bp); }
   void _xadd(Operand *Dest, Variable *Src, bool Locked) {
     AutoMemorySandboxer<> _(this, &Dest, &Src);
     Context.insert<typename Traits::Insts::Xadd>(Dest, Src, Locked);
     // The xadd exchanges Dest and Src (modifying Src). Model that update with
     // a FakeDef followed by a FakeUse.
     Context.insert<InstFakeDef>(Src, llvm::dyn_cast<Variable>(Dest));
     _set_dest_redefined();
     Context.insert<InstFakeUse>(Src);
   }
   void _xchg(Operand *Dest, Variable *Src) {
@@ skipping 156 matching lines @@
 
   static FixupKind PcRelFixup;
   static FixupKind AbsFixup;
 };
 } // end of namespace X86NAMESPACE
 } // end of namespace Ice
 
 #include "IceTargetLoweringX86BaseImpl.h"
 
 #endif // SUBZERO_SRC_ICETARGETLOWERINGX86BASE_H