Subzero. X8664. Enables RIP-based addressing mode.

src/IceAssemblerX86BaseImpl.h

 //===- subzero/src/IceAssemblerX86BaseImpl.h - base x86 assembler -*- C++ -*-=//
 // Copyright (c) 2013, the Dart project authors.  Please see the AUTHORS file
 // for details. All rights reserved. Use of this source code is governed by a
 // BSD-style license that can be found in the LICENSE file.
 //
 // Modified by the Subzero authors.
 //
 //===----------------------------------------------------------------------===//
 //
 //                        The Subzero Code Generator
@@ skipping 281 matching lines @@
 void AssemblerX86Base<TraitsType>::mov(Type Ty, const Address &dst,
                                        const Immediate &imm) {
   assert(Ty != IceType_i64 && "i64 not supported yet.");
   AssemblerBuffer::EnsureCapacity ensured(&Buffer);
   if (Ty == IceType_i16)
     emitOperandSizeOverride();
   emitAddrSizeOverridePrefix();
   emitRex(Ty, dst, RexRegIrrelevant);
   if (isByteSizedType(Ty)) {
     emitUint8(0xC6);
-    emitOperand(0, dst);
+    static constexpr RelocOffsetT OffsetFromNextInstruction = 1;

[Jim Stichnoth, 2016/01/23 01:57:46]

What do you think about using typeWidthInBytes(Ty) in this method?

[John, 2016/01/26 19:44:25]

Discussed offline. keeping as is.

+    emitOperand(0, dst, OffsetFromNextInstruction);
     emitUint8(imm.value() & 0xFF);
   } else {
     emitUint8(0xC7);
-    emitOperand(0, dst);
+    const uint8_t OffsetFromNextInstruction = Ty == IceType_i16 ? 2 : 4;
+    emitOperand(0, dst, OffsetFromNextInstruction);
     emitImmediate(Ty, imm);
   }
 }
 
 template <typename TraitsType>
 template <typename T>
 typename std::enable_if<T::Is64Bit, void>::type
 AssemblerX86Base<TraitsType>::movabs(const GPRRegister Dst, uint64_t Imm64) {
   AssemblerBuffer::EnsureCapacity ensured(&Buffer);
   const bool NeedsRexW = (Imm64 & ~0xFFFFFFFFull) != 0;
@@ skipping 1105 matching lines @@
 void AssemblerX86Base<TraitsType>::cmpps(Type Ty, XmmRegister dst,
                                          const Address &src,
                                          CmppsCond CmpCondition) {
   AssemblerBuffer::EnsureCapacity ensured(&Buffer);
   if (Ty == IceType_f64)
     emitUint8(0x66);
   emitAddrSizeOverridePrefix();
   emitRex(RexTypeIrrelevant, src, dst);
   emitUint8(0x0F);
   emitUint8(0xC2);
-  emitOperand(gprEncoding(dst), src);
+  static constexpr RelocOffsetT OffsetFromNextInstruction = 1;
+  emitOperand(gprEncoding(dst), src, OffsetFromNextInstruction);
   emitUint8(CmpCondition);
 }
 
 template <typename TraitsType>
 void AssemblerX86Base<TraitsType>::sqrtps(XmmRegister dst) {
   AssemblerBuffer::EnsureCapacity ensured(&Buffer);
   emitRexRB(RexTypeIrrelevant, dst, dst);
   emitUint8(0x0F);
   emitUint8(0x51);
   emitXmmRegisterOperand(dst, dst);
@@ skipping 101 matching lines @@
 template <typename TraitsType>
 void AssemblerX86Base<TraitsType>::pshufd(Type /* Ty */, XmmRegister dst,
                                           const Address &src,
                                           const Immediate &imm) {
   AssemblerBuffer::EnsureCapacity ensured(&Buffer);
   emitUint8(0x66);
   emitAddrSizeOverridePrefix();
   emitRex(RexTypeIrrelevant, src, dst);
   emitUint8(0x0F);
   emitUint8(0x70);
-  emitOperand(gprEncoding(dst), src);
+  static constexpr RelocOffsetT OffsetFromNextInstruction = 1;
+  emitOperand(gprEncoding(dst), src, OffsetFromNextInstruction);
   assert(imm.is_uint8());
   emitUint8(imm.value());
 }
 
 template <typename TraitsType>
 void AssemblerX86Base<TraitsType>::shufps(Type /* Ty */, XmmRegister dst,
                                           XmmRegister src,
                                           const Immediate &imm) {
   AssemblerBuffer::EnsureCapacity ensured(&Buffer);
   emitRexRB(RexTypeIrrelevant, dst, src);
   emitUint8(0x0F);
   emitUint8(0xC6);
   emitXmmRegisterOperand(dst, src);
   assert(imm.is_uint8());
   emitUint8(imm.value());
 }
 
 template <typename TraitsType>
 void AssemblerX86Base<TraitsType>::shufps(Type /* Ty */, XmmRegister dst,
                                           const Address &src,
                                           const Immediate &imm) {
   AssemblerBuffer::EnsureCapacity ensured(&Buffer);
   emitAddrSizeOverridePrefix();
   emitRex(RexTypeIrrelevant, src, dst);
   emitUint8(0x0F);
   emitUint8(0xC6);
-  emitOperand(gprEncoding(dst), src);
+  static constexpr RelocOffsetT OffsetFromNextInstruction = 1;
+  emitOperand(gprEncoding(dst), src, OffsetFromNextInstruction);
   assert(imm.is_uint8());
   emitUint8(imm.value());
 }
 
 template <typename TraitsType>
 void AssemblerX86Base<TraitsType>::sqrtpd(XmmRegister dst) {
   AssemblerBuffer::EnsureCapacity ensured(&Buffer);
   emitUint8(0x66);
   emitRexRB(RexTypeIrrelevant, dst, dst);
   emitUint8(0x0F);
@@ skipping 231 matching lines @@
   AssemblerBuffer::EnsureCapacity ensured(&Buffer);
   assert(imm.is_uint8());
   assert(isVectorFloatingType(Ty));
   (void)Ty;
   emitUint8(0x66);
   emitAddrSizeOverridePrefix();
   emitRex(RexTypeIrrelevant, src, dst);
   emitUint8(0x0F);
   emitUint8(0x3A);
   emitUint8(0x21);
-  emitOperand(gprEncoding(dst), src);
+  static constexpr RelocOffsetT OffsetFromNextInstruction = 1;
+  emitOperand(gprEncoding(dst), src, OffsetFromNextInstruction);
   emitUint8(imm.value());
 }
 
 template <typename TraitsType>
 void AssemblerX86Base<TraitsType>::pinsr(Type Ty, XmmRegister dst,
                                          GPRRegister src,
                                          const Immediate &imm) {
   AssemblerBuffer::EnsureCapacity ensured(&Buffer);
   assert(imm.is_uint8());
   emitUint8(0x66);
@@ skipping 18 matching lines @@
   emitUint8(0x66);
   emitAddrSizeOverridePrefix();
   emitRex(RexTypeIrrelevant, src, dst);
   emitUint8(0x0F);
   if (Ty == IceType_i16) {
     emitUint8(0xC4);
   } else {
     emitUint8(0x3A);
     emitUint8(isByteSizedType(Ty) ? 0x20 : 0x22);
   }
-  emitOperand(gprEncoding(dst), src);
+  static constexpr RelocOffsetT OffsetFromNextInstruction = 1;
+  emitOperand(gprEncoding(dst), src, OffsetFromNextInstruction);
   emitUint8(imm.value());
 }
 
 template <typename TraitsType>
 void AssemblerX86Base<TraitsType>::pextr(Type Ty, GPRRegister dst,
                                          XmmRegister src,
                                          const Immediate &imm) {
   AssemblerBuffer::EnsureCapacity ensured(&Buffer);
   assert(imm.is_uint8());
   if (Ty == IceType_i16) {
@@ skipping 354 matching lines @@
 void AssemblerX86Base<TraitsType>::test(Type Ty, const Address &addr,
                                         const Immediate &immediate) {
   AssemblerBuffer::EnsureCapacity ensured(&Buffer);
   // If the immediate is short, we only test the byte addr to keep the encoding
   // short.
   if (immediate.is_uint8()) {
     // Use zero-extended 8-bit immediate.
     emitAddrSizeOverridePrefix();
     emitRex(Ty, addr, RexRegIrrelevant);
     emitUint8(0xF6);
-    emitOperand(0, addr);
+    static constexpr RelocOffsetT OffsetFromNextInstruction = 1;
+    emitOperand(0, addr, OffsetFromNextInstruction);
     emitUint8(immediate.value() & 0xFF);
   } else {
     if (Ty == IceType_i16)
       emitOperandSizeOverride();
     emitAddrSizeOverridePrefix();
     emitRex(Ty, addr, RexRegIrrelevant);
     emitUint8(0xF7);
-    emitOperand(0, addr);
+    const uint8_t OffsetFromNextInstruction = Ty == IceType_i16 ? 2 : 4;
+    emitOperand(0, addr, OffsetFromNextInstruction);
     emitImmediate(Ty, immediate);
   }
 }
 
 template <typename TraitsType>
 void AssemblerX86Base<TraitsType>::And(Type Ty, GPRRegister dst,
                                        GPRRegister src) {
   arith_int<4>(Ty, dst, src);
 }
 
@@ skipping 380 matching lines @@
                                         const Address &address,
                                         const Immediate &imm) {
   AssemblerBuffer::EnsureCapacity ensured(&Buffer);
   assert(Ty == IceType_i16 || Ty == IceType_i32);
   if (Ty == IceType_i16)
     emitOperandSizeOverride();
   emitAddrSizeOverridePrefix();
   emitRex(Ty, address, dst);
   if (imm.is_int8()) {
     emitUint8(0x6B);
-    emitOperand(gprEncoding(dst), address);
+    static constexpr RelocOffsetT OffsetFromNextInstruction = 1;
+    emitOperand(gprEncoding(dst), address, OffsetFromNextInstruction);
     emitUint8(imm.value() & 0xFF);
   } else {
     emitUint8(0x69);
-    emitOperand(gprEncoding(dst), address);
+    const uint8_t OffsetFromNextInstruction = Ty == IceType_i16 ? 2 : 4;
+    emitOperand(gprEncoding(dst), address, OffsetFromNextInstruction);
     emitImmediate(Ty, imm);
   }
 }
 
 template <typename TraitsType>
 void AssemblerX86Base<TraitsType>::mul(Type Ty, GPRRegister reg) {
   AssemblerBuffer::EnsureCapacity ensured(&Buffer);
   if (Ty == IceType_i16)
     emitOperandSizeOverride();
   emitRexB(Ty, reg);
@@ skipping 668 matching lines @@
   while (L->hasNear()) {
     intptr_t Position = L->getNearPosition();
     const intptr_t Offset = Bound - (Position + 1);
     assert(Utils::IsInt(8, Offset));
     Buffer.store<int8_t>(Position, Offset);
   }
   L->bindTo(Bound);
 }
 
 template <typename TraitsType>
-void AssemblerX86Base<TraitsType>::emitOperand(int rm, const Operand &operand) {
+void AssemblerX86Base<TraitsType>::emitOperand(int rm, const Operand &operand,
+                                               RelocOffsetT Addend) {
   assert(rm >= 0 && rm < 8);
   const intptr_t length = operand.length_;
   assert(length > 0);
   intptr_t displacement_start = 1;
   // Emit the ModRM byte updated with the given RM value.
   assert((operand.encoding_[0] & 0x38) == 0);
   emitUint8(operand.encoding_[0] + (rm << 3));
   // Whenever the addressing mode is not register indirect, using esp == 0x4
   // as the register operation indicates an SIB byte follows.
   if (((operand.encoding_[0] & 0xc0) != 0xc0) &&
       ((operand.encoding_[0] & 0x07) == 0x04)) {
     emitUint8(operand.encoding_[1]);
     displacement_start = 2;
   }
   // Emit the displacement and the fixup that affects it, if any.
-  if (operand.fixup()) {
-    emitFixup(operand.fixup());
+  AssemblerFixup *Fixup = operand.fixup();
+  if (Fixup != nullptr) {
+    emitFixup(Fixup);
     assert(length - displacement_start == 4);
+    if (fixupIsPCRel(Fixup->kind())) {
+      Fixup->set_addend(-Addend);
+      int32_t Offset;
+      memmove(&Offset, &operand.encoding_[displacement_start], sizeof(Offset));
+      Offset -= Addend;
+      emitInt32(Offset);
+      return;
+    }
   }
   for (intptr_t i = displacement_start; i < length; i++) {
     emitUint8(operand.encoding_[i]);
   }
 }
 
 template <typename TraitsType>
 void AssemblerX86Base<TraitsType>::emitImmediate(Type Ty,
                                                  const Immediate &imm) {
+  auto *const Fixup = imm.fixup();

[Jim Stichnoth, 2016/01/23 01:57:46]

Fortunately I didn't have to scan too far from here to figure out what Fixup's
type is...

[John, 2016/01/26 19:44:25]

My arguments for auto here:

1) the following line

AssemblerFixup *const Fixup = imm.fixup();

contains way too many "fixups" in it. (dummy reason, I know, but it is still
valid. :P)

2)  Fixup is not really used here for anything, except to cache imm.fixup(). The
previous code used imm.fixup() as a function argument, ergo the return type was
not known to being with. auto here is not making anything worse than the call

emitFixup(imm.fixup()); // what's typedecl(imm.fixup())?

3) auto is great for "throw away" temporaries like this. I personally refrain
from using temporaries to cache function return values simply because I don't
want to spell out types.

   if (Ty == IceType_i16) {
-    assert(!imm.fixup());
+    assert(Fixup == nullptr);
     emitInt16(imm.value());
-  } else {
-    if (imm.fixup()) {
-      emitFixup(imm.fixup());
-    }
-    emitInt32(imm.value());
+    return;
   }
+
+  if (Fixup != nullptr) {
+    emitFixup(Fixup);
+  }
+  emitInt32(imm.value());
 }
 
 template <typename TraitsType>
 void AssemblerX86Base<TraitsType>::emitComplexI8(int rm, const Operand &operand,
                                                  const Immediate &immediate) {
   assert(rm >= 0 && rm < 8);
   assert(immediate.is_int8());
   if (operand.IsRegister(Traits::Encoded_Reg_Accumulator)) {
     // Use short form if the destination is al.
     emitUint8(0x04 + (rm << 3));
     emitUint8(immediate.value() & 0xFF);
   } else {
     // Use sign-extended 8-bit immediate.
     emitUint8(0x80);
-    emitOperand(rm, operand);
+    static constexpr RelocOffsetT OffsetFromNextInstruction = 1;
+    emitOperand(rm, operand, OffsetFromNextInstruction);
     emitUint8(immediate.value() & 0xFF);
   }
 }
 
 template <typename TraitsType>
 void AssemblerX86Base<TraitsType>::emitComplex(Type Ty, int rm,
                                                const Operand &operand,
                                                const Immediate &immediate) {
   assert(rm >= 0 && rm < 8);
   if (immediate.is_int8()) {
     // Use sign-extended 8-bit immediate.
     emitUint8(0x83);
-    emitOperand(rm, operand);
+    static constexpr RelocOffsetT OffsetFromNextInstruction = 1;
+    emitOperand(rm, operand, OffsetFromNextInstruction);
     emitUint8(immediate.value() & 0xFF);
   } else if (operand.IsRegister(Traits::Encoded_Reg_Accumulator)) {
     // Use short form if the destination is eax.
     emitUint8(0x05 + (rm << 3));
     emitImmediate(Ty, immediate);
   } else {
     emitUint8(0x81);
-    emitOperand(rm, operand);
+    const uint8_t OffsetFromNextInstruction = Ty == IceType_i16 ? 2 : 4;
+    emitOperand(rm, operand, OffsetFromNextInstruction);
     emitImmediate(Ty, immediate);
   }
 }
 
 template <typename TraitsType>
 void AssemblerX86Base<TraitsType>::emitLabel(Label *label,
                                              intptr_t instruction_size) {
   if (label->isBound()) {
     intptr_t offset = label->getPosition() - Buffer.size();
     assert(offset <= 0);
@@ skipping 29 matching lines @@
   // same processor behavior regardless of whether it's an immediate (masked to
   // 8 bits) or in register cl (essentially ecx masked to 8 bits).
   if (Ty == IceType_i16)
     emitOperandSizeOverride();
   emitRexB(Ty, reg);
   if (imm.value() == 1) {
     emitUint8(isByteSizedArithType(Ty) ? 0xD0 : 0xD1);
     emitOperand(rm, Operand(reg));
   } else {
     emitUint8(isByteSizedArithType(Ty) ? 0xC0 : 0xC1);
-    emitOperand(rm, Operand(reg));
+    static constexpr RelocOffsetT OffsetFromNextInstruction = 1;
+    emitOperand(rm, Operand(reg), OffsetFromNextInstruction);
     emitUint8(imm.value() & 0xFF);
   }
 }
 
 template <typename TraitsType>
 void AssemblerX86Base<TraitsType>::emitGenericShift(int rm, Type Ty,
                                                     const Operand &operand,
                                                     GPRRegister shifter) {
   AssemblerBuffer::EnsureCapacity ensured(&Buffer);
   assert(shifter == Traits::Encoded_Reg_Counter);
   (void)shifter;
   if (Ty == IceType_i16)
     emitOperandSizeOverride();
   emitRexB(Ty, operand.rm());
   emitUint8(isByteSizedArithType(Ty) ? 0xD2 : 0xD3);
   emitOperand(rm, operand);
 }
 
 } // end of namespace X86NAMESPACE
 } // end of namespace Ice