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1 //===- subzero/src/IceTargetLoweringX86Base.h - x86 lowering ----*- C++ -*-===// | 1 //===- subzero/src/IceTargetLoweringX86Base.h - x86 lowering ----*- C++ -*-===// |
2 // | 2 // |
3 // The Subzero Code Generator | 3 // The Subzero Code Generator |
4 // | 4 // |
5 // This file is distributed under the University of Illinois Open Source | 5 // This file is distributed under the University of Illinois Open Source |
6 // License. See LICENSE.TXT for details. | 6 // License. See LICENSE.TXT for details. |
7 // | 7 // |
8 //===----------------------------------------------------------------------===// | 8 //===----------------------------------------------------------------------===// |
9 /// | 9 /// |
10 /// \file | 10 /// \file |
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89 void translateOm1() override; | 89 void translateOm1() override; |
90 void translateO2() override; | 90 void translateO2() override; |
91 void doLoadOpt(); | 91 void doLoadOpt(); |
92 bool doBranchOpt(Inst *I, const CfgNode *NextNode) override; | 92 bool doBranchOpt(Inst *I, const CfgNode *NextNode) override; |
93 | 93 |
94 SizeT getNumRegisters() const override { | 94 SizeT getNumRegisters() const override { |
95 return Traits::RegisterSet::Reg_NUM; | 95 return Traits::RegisterSet::Reg_NUM; |
96 } | 96 } |
97 Variable *getPhysicalRegister(SizeT RegNum, Type Ty = IceType_void) override; | 97 Variable *getPhysicalRegister(SizeT RegNum, Type Ty = IceType_void) override; |
98 IceString getRegName(SizeT RegNum, Type Ty) const override; | 98 IceString getRegName(SizeT RegNum, Type Ty) const override; |
| 99 static IceString getRegClassName(RegClass C) { |
| 100 auto ClassNum = static_cast<RegClassX86>(C); |
| 101 assert(ClassNum < RCX86_NUM); |
| 102 switch (ClassNum) { |
| 103 default: |
| 104 assert(C < RC_Target); |
| 105 return regClassString(C); |
| 106 case RCX86_Is64To8: |
| 107 return "i64to8"; // 64-bit GPR truncable to i8 |
| 108 case RCX86_Is32To8: |
| 109 return "i32to8"; // 32-bit GPR truncable to i8 |
| 110 case RCX86_Is16To8: |
| 111 return "i16to8"; // 16-bit GPR truncable to i8 |
| 112 case RCX86_IsTrunc8Rcvr: |
| 113 return "i8from"; // 8-bit GPR truncable from wider GPRs |
| 114 case RCX86_IsAhRcvr: |
| 115 return "i8fromah"; // 8-bit GPR that ah can be assigned to |
| 116 } |
| 117 } |
99 llvm::SmallBitVector getRegisterSet(RegSetMask Include, | 118 llvm::SmallBitVector getRegisterSet(RegSetMask Include, |
100 RegSetMask Exclude) const override; | 119 RegSetMask Exclude) const override; |
101 const llvm::SmallBitVector & | 120 const llvm::SmallBitVector & |
102 getRegistersForVariable(const Variable *Var) const override { | 121 getRegistersForVariable(const Variable *Var) const override { |
103 RegClass RC = Var->getRegClass(); | 122 RegClass RC = Var->getRegClass(); |
104 assert(static_cast<RegClassX86>(RC) < RCX86_NUM); | 123 assert(static_cast<RegClassX86>(RC) < RCX86_NUM); |
105 return TypeToRegisterSet[RC]; | 124 return TypeToRegisterSet[RC]; |
106 } | 125 } |
107 | 126 |
108 const llvm::SmallBitVector &getAliasesForRegister(SizeT Reg) const override { | 127 const llvm::SmallBitVector &getAliasesForRegister(SizeT Reg) const override { |
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1019 | 1038 |
1020 static FixupKind PcRelFixup; | 1039 static FixupKind PcRelFixup; |
1021 static FixupKind AbsFixup; | 1040 static FixupKind AbsFixup; |
1022 }; | 1041 }; |
1023 } // end of namespace X86NAMESPACE | 1042 } // end of namespace X86NAMESPACE |
1024 } // end of namespace Ice | 1043 } // end of namespace Ice |
1025 | 1044 |
1026 #include "IceTargetLoweringX86BaseImpl.h" | 1045 #include "IceTargetLoweringX86BaseImpl.h" |
1027 | 1046 |
1028 #endif // SUBZERO_SRC_ICETARGETLOWERINGX86BASE_H | 1047 #endif // SUBZERO_SRC_ICETARGETLOWERINGX86BASE_H |
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