Subzero: Make -reg-use and -reg-exclude specific to register class.

src/IceTargetLoweringARM32.cpp

 //===- subzero/src/IceTargetLoweringARM32.cpp - ARM32 lowering ------------===//
 //
 //                        The Subzero Code Generator
 //
 // This file is distributed under the University of Illinois Open Source
 // License. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
 ///
 /// \file
@@ skipping 253 matching lines @@
 std::array<uint32_t, NumFP64Args> FP64ArgInitializer;
 
 constexpr SizeT NumVec128Args =
 #define X(val, encode, name, cc_arg, scratch, preserved, stackptr, frameptr,   \
           isGPR, isInt, isI64Pair, isFP32, isFP64, isVec128, alias_init)       \
   +(((cc_arg > 0)) ? 1 : 0)
     REGARM32_VEC128_TABLE
 #undef X
     ;
 std::array<uint32_t, NumVec128Args> Vec128ArgInitializer;
+
+IceString getRegClassName(RegClass C) {
+  auto ClassNum = static_cast<RegARM32::RegClassARM32>(C);
+  assert(ClassNum < RegARM32::RCARM32_NUM);
+  switch (ClassNum) {
+  default:
+    assert(C < RC_Target);
+    return regClassString(C);
+    // Add handling of new register classes below.
+  }
+}
+
 } // end of anonymous namespace
 
 TargetARM32::TargetARM32(Cfg *Func)
     : TargetLowering(Func), NeedSandboxing(Ctx->getFlags().getUseSandboxing()),
       CPUFeatures(Func->getContext()->getFlags()) {}
 
 void TargetARM32::staticInit(GlobalContext *Ctx) {
 
   // Limit this size (or do all bitsets need to be the same width)???
   llvm::SmallBitVector IntegerRegisters(RegARM32::Reg_NUM);
@@ skipping 40 matching lines @@
   TypeToRegisterSet[IceType_f64] = Float64Registers;
   TypeToRegisterSet[IceType_v4i1] = VectorRegisters;
   TypeToRegisterSet[IceType_v8i1] = VectorRegisters;
   TypeToRegisterSet[IceType_v16i1] = VectorRegisters;
   TypeToRegisterSet[IceType_v16i8] = VectorRegisters;
   TypeToRegisterSet[IceType_v8i16] = VectorRegisters;
   TypeToRegisterSet[IceType_v4i32] = VectorRegisters;
   TypeToRegisterSet[IceType_v4f32] = VectorRegisters;
 
   filterTypeToRegisterSet(
-      Ctx, RegARM32::Reg_NUM, TypeToRegisterSet, RegARM32::RCARM32_NUM,
-      [](int32_t RegNum) -> IceString {
+      Ctx, RegARM32::Reg_NUM, TypeToRegisterSet,
+      llvm::array_lengthof(TypeToRegisterSet), [](int32_t RegNum) -> IceString {
+        // This function simply removes ", " from the register name.
         IceString Name = RegARM32::getRegName(RegNum);
         constexpr const char RegSeparator[] = ", ";
         constexpr size_t RegSeparatorWidth =
             llvm::array_lengthof(RegSeparator) - 1;
         for (size_t Pos = Name.find(RegSeparator); Pos != std::string::npos;
              Pos = Name.find(RegSeparator)) {
-          Name.replace(Pos, RegSeparatorWidth, ":");
+          Name.replace(Pos, RegSeparatorWidth, "");
         }
         return Name;
-      });
+      }, getRegClassName);
 }
 
 namespace {
 void copyRegAllocFromInfWeightVariable64On32(const VarList &Vars) {
   for (Variable *Var : Vars) {
     auto *Var64 = llvm::dyn_cast<Variable64On32>(Var);
     if (!Var64) {
       // This is not the variable we are looking for.
       continue;
     }
@@ skipping 6092 matching lines @@
       << ".eabi_attribute 42, 1   @ Tag_MPextension_use\n"
       << ".eabi_attribute 68, 1   @ Tag_Virtualization_use\n";
   if (CPUFeatures.hasFeature(TargetARM32Features::HWDivArm)) {
     Str << ".eabi_attribute 44, 2   @ Tag_DIV_use\n";
   }
   // Technically R9 is used for TLS with Sandboxing, and we reserve it.
   // However, for compatibility with current NaCl LLVM, don't claim that.
   Str << ".eabi_attribute 14, 3   @ Tag_ABI_PCS_R9_use: Not used\n";
 }
 
-llvm::SmallBitVector TargetARM32::TypeToRegisterSet[IceType_NUM];
+llvm::SmallBitVector TargetARM32::TypeToRegisterSet[RegARM32::RCARM32_NUM];
 llvm::SmallBitVector TargetARM32::RegisterAliases[RegARM32::Reg_NUM];
 
 } // end of namespace ARM32
 } // end of namespace Ice