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| 1 //===- subzero/src/IceTargetLoweringX86Base.h - x86 lowering ----*- C++ -*-===// | 1 //===- subzero/src/IceTargetLoweringX86Base.h - x86 lowering ----*- C++ -*-===// |
| 2 // | 2 // |
| 3 // The Subzero Code Generator | 3 // The Subzero Code Generator |
| 4 // | 4 // |
| 5 // This file is distributed under the University of Illinois Open Source | 5 // This file is distributed under the University of Illinois Open Source |
| 6 // License. See LICENSE.TXT for details. | 6 // License. See LICENSE.TXT for details. |
| 7 // | 7 // |
| 8 //===----------------------------------------------------------------------===// | 8 //===----------------------------------------------------------------------===// |
| 9 /// | 9 /// |
| 10 /// \file | 10 /// \file |
| (...skipping 78 matching lines...) Expand 10 before | Expand all | Expand 10 after Loading... |
| 89 void translateOm1() override; | 89 void translateOm1() override; |
| 90 void translateO2() override; | 90 void translateO2() override; |
| 91 void doLoadOpt(); | 91 void doLoadOpt(); |
| 92 bool doBranchOpt(Inst *I, const CfgNode *NextNode) override; | 92 bool doBranchOpt(Inst *I, const CfgNode *NextNode) override; |
| 93 | 93 |
| 94 SizeT getNumRegisters() const override { | 94 SizeT getNumRegisters() const override { |
| 95 return Traits::RegisterSet::Reg_NUM; | 95 return Traits::RegisterSet::Reg_NUM; |
| 96 } | 96 } |
| 97 Variable *getPhysicalRegister(SizeT RegNum, Type Ty = IceType_void) override; | 97 Variable *getPhysicalRegister(SizeT RegNum, Type Ty = IceType_void) override; |
| 98 IceString getRegName(SizeT RegNum, Type Ty) const override; | 98 IceString getRegName(SizeT RegNum, Type Ty) const override; |
| 99 static IceString getRegClassName(RegClass C) { |
| 100 auto ClassNum = static_cast<RegClassX86>(C); |
| 101 assert(ClassNum < RCX86_NUM); |
| 102 switch (ClassNum) { |
| 103 default: |
| 104 return regClassString(C); |
| 105 case RCX86_Is64To8: |
| 106 return "i64to8"; // 64-bit GPR truncable to i8 |
| 107 case RCX86_Is32To8: |
| 108 return "i32to8"; // 32-bit GPR truncable to i8 |
| 109 case RCX86_Is16To8: |
| 110 return "i16to8"; // 16-bit GPR truncable to i8 |
| 111 case RCX86_IsTrunc8Rcvr: |
| 112 return "i8from"; // 8-bit GPR truncable from wider GPRs |
| 113 case RCX86_IsAhRcvr: |
| 114 return "i8fromah"; // 8-bit GPR that ah can be assigned to |
| 115 } |
| 116 } |
| 99 llvm::SmallBitVector getRegisterSet(RegSetMask Include, | 117 llvm::SmallBitVector getRegisterSet(RegSetMask Include, |
| 100 RegSetMask Exclude) const override; | 118 RegSetMask Exclude) const override; |
| 101 const llvm::SmallBitVector & | 119 const llvm::SmallBitVector & |
| 102 getRegistersForVariable(const Variable *Var) const override { | 120 getRegistersForVariable(const Variable *Var) const override { |
| 103 RegClass RC = Var->getRegClass(); | 121 RegClass RC = Var->getRegClass(); |
| 104 assert(static_cast<RegClassX86>(RC) < RCX86_NUM); | 122 assert(static_cast<RegClassX86>(RC) < RCX86_NUM); |
| 105 return TypeToRegisterSet[RC]; | 123 return TypeToRegisterSet[RC]; |
| 106 } | 124 } |
| 107 | 125 |
| 108 const llvm::SmallBitVector &getAliasesForRegister(SizeT Reg) const override { | 126 const llvm::SmallBitVector &getAliasesForRegister(SizeT Reg) const override { |
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| 1019 | 1037 |
| 1020 static FixupKind PcRelFixup; | 1038 static FixupKind PcRelFixup; |
| 1021 static FixupKind AbsFixup; | 1039 static FixupKind AbsFixup; |
| 1022 }; | 1040 }; |
| 1023 } // end of namespace X86NAMESPACE | 1041 } // end of namespace X86NAMESPACE |
| 1024 } // end of namespace Ice | 1042 } // end of namespace Ice |
| 1025 | 1043 |
| 1026 #include "IceTargetLoweringX86BaseImpl.h" | 1044 #include "IceTargetLoweringX86BaseImpl.h" |
| 1027 | 1045 |
| 1028 #endif // SUBZERO_SRC_ICETARGETLOWERINGX86BASE_H | 1046 #endif // SUBZERO_SRC_ICETARGETLOWERINGX86BASE_H |
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