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| 1 //===- subzero/src/IceTargetLoweringX8632Traits.h - x86-32 traits -*- C++ -*-=// | 1 //===- subzero/src/IceTargetLoweringX8632Traits.h - x86-32 traits -*- C++ -*-=// |
| 2 // | 2 // |
| 3 // The Subzero Code Generator | 3 // The Subzero Code Generator |
| 4 // | 4 // |
| 5 // This file is distributed under the University of Illinois Open Source | 5 // This file is distributed under the University of Illinois Open Source |
| 6 // License. See LICENSE.TXT for details. | 6 // License. See LICENSE.TXT for details. |
| 7 // | 7 // |
| 8 //===----------------------------------------------------------------------===// | 8 //===----------------------------------------------------------------------===// |
| 9 /// | 9 /// |
| 10 /// \file | 10 /// \file |
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| 509 (*RegisterAliases)[Entry.Val].set(Alias); | 509 (*RegisterAliases)[Entry.Val].set(Alias); |
| 510 } | 510 } |
| 511 (*RegisterAliases)[Entry.Val].set(Entry.Val); | 511 (*RegisterAliases)[Entry.Val].set(Entry.Val); |
| 512 } | 512 } |
| 513 | 513 |
| 514 (*TypeToRegisterSet)[RC_void] = InvalidRegisters; | 514 (*TypeToRegisterSet)[RC_void] = InvalidRegisters; |
| 515 (*TypeToRegisterSet)[RC_i1] = IntegerRegistersI8; | 515 (*TypeToRegisterSet)[RC_i1] = IntegerRegistersI8; |
| 516 (*TypeToRegisterSet)[RC_i8] = IntegerRegistersI8; | 516 (*TypeToRegisterSet)[RC_i8] = IntegerRegistersI8; |
| 517 (*TypeToRegisterSet)[RC_i16] = IntegerRegistersI16; | 517 (*TypeToRegisterSet)[RC_i16] = IntegerRegistersI16; |
| 518 (*TypeToRegisterSet)[RC_i32] = IntegerRegistersI32; | 518 (*TypeToRegisterSet)[RC_i32] = IntegerRegistersI32; |
| 519 (*TypeToRegisterSet)[RC_i64] = IntegerRegistersI32; | 519 (*TypeToRegisterSet)[RC_i64] = InvalidRegisters; |
| 520 (*TypeToRegisterSet)[RC_f32] = FloatRegisters; | 520 (*TypeToRegisterSet)[RC_f32] = FloatRegisters; |
| 521 (*TypeToRegisterSet)[RC_f64] = FloatRegisters; | 521 (*TypeToRegisterSet)[RC_f64] = FloatRegisters; |
| 522 (*TypeToRegisterSet)[RC_v4i1] = VectorRegisters; | 522 (*TypeToRegisterSet)[RC_v4i1] = VectorRegisters; |
| 523 (*TypeToRegisterSet)[RC_v8i1] = VectorRegisters; | 523 (*TypeToRegisterSet)[RC_v8i1] = VectorRegisters; |
| 524 (*TypeToRegisterSet)[RC_v16i1] = VectorRegisters; | 524 (*TypeToRegisterSet)[RC_v16i1] = VectorRegisters; |
| 525 (*TypeToRegisterSet)[RC_v16i8] = VectorRegisters; | 525 (*TypeToRegisterSet)[RC_v16i8] = VectorRegisters; |
| 526 (*TypeToRegisterSet)[RC_v8i16] = VectorRegisters; | 526 (*TypeToRegisterSet)[RC_v8i16] = VectorRegisters; |
| 527 (*TypeToRegisterSet)[RC_v4i32] = VectorRegisters; | 527 (*TypeToRegisterSet)[RC_v4i32] = VectorRegisters; |
| 528 (*TypeToRegisterSet)[RC_v4f32] = VectorRegisters; | 528 (*TypeToRegisterSet)[RC_v4f32] = VectorRegisters; |
| 529 (*TypeToRegisterSet)[RCX86_Is64To8] = Trunc64To8Registers; | 529 (*TypeToRegisterSet)[RCX86_Is64To8] = Trunc64To8Registers; |
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| 988 | 988 |
| 989 static uint8_t InstSegmentPrefixes[]; | 989 static uint8_t InstSegmentPrefixes[]; |
| 990 }; | 990 }; |
| 991 | 991 |
| 992 using Traits = ::Ice::X8632::TargetX8632Traits; | 992 using Traits = ::Ice::X8632::TargetX8632Traits; |
| 993 } // end of namespace X8632 | 993 } // end of namespace X8632 |
| 994 | 994 |
| 995 } // end of namespace Ice | 995 } // end of namespace Ice |
| 996 | 996 |
| 997 #endif // SUBZERO_SRC_ICETARGETLOWERINGX8632TRAITS_H | 997 #endif // SUBZERO_SRC_ICETARGETLOWERINGX8632TRAITS_H |
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