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Side by Side Diff: src/IceTargetLoweringMIPS32.cpp

Issue 1614273002: Subzero: Make -reg-use and -reg-exclude specific to register class. (Closed) Base URL: https://chromium.googlesource.com/native_client/pnacl-subzero.git@master
Patch Set: Cleanup Created 4 years, 11 months ago
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1 //===- subzero/src/IceTargetLoweringMIPS32.cpp - MIPS32 lowering ----------===// 1 //===- subzero/src/IceTargetLoweringMIPS32.cpp - MIPS32 lowering ----------===//
2 // 2 //
3 // The Subzero Code Generator 3 // The Subzero Code Generator
4 // 4 //
5 // This file is distributed under the University of Illinois Open Source 5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details. 6 // License. See LICENSE.TXT for details.
7 // 7 //
8 //===----------------------------------------------------------------------===// 8 //===----------------------------------------------------------------------===//
9 /// 9 ///
10 /// \file 10 /// \file
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99 TypeToRegisterSet[IceType_f64] = Float64Registers; 99 TypeToRegisterSet[IceType_f64] = Float64Registers;
100 TypeToRegisterSet[IceType_v4i1] = VectorRegisters; 100 TypeToRegisterSet[IceType_v4i1] = VectorRegisters;
101 TypeToRegisterSet[IceType_v8i1] = VectorRegisters; 101 TypeToRegisterSet[IceType_v8i1] = VectorRegisters;
102 TypeToRegisterSet[IceType_v16i1] = VectorRegisters; 102 TypeToRegisterSet[IceType_v16i1] = VectorRegisters;
103 TypeToRegisterSet[IceType_v16i8] = VectorRegisters; 103 TypeToRegisterSet[IceType_v16i8] = VectorRegisters;
104 TypeToRegisterSet[IceType_v8i16] = VectorRegisters; 104 TypeToRegisterSet[IceType_v8i16] = VectorRegisters;
105 TypeToRegisterSet[IceType_v4i32] = VectorRegisters; 105 TypeToRegisterSet[IceType_v4i32] = VectorRegisters;
106 TypeToRegisterSet[IceType_v4f32] = VectorRegisters; 106 TypeToRegisterSet[IceType_v4f32] = VectorRegisters;
107 107
108 filterTypeToRegisterSet(Ctx, RegMIPS32::Reg_NUM, TypeToRegisterSet, 108 filterTypeToRegisterSet(Ctx, RegMIPS32::Reg_NUM, TypeToRegisterSet,
109 RCMIPS32_NUM, [](int32_t RegNum) -> IceString { 109 RCMIPS32_NUM, RegMIPS32::getRegName, regClassString);
Karl 2016/01/22 17:10:54 Like in the ARM case, I would add an assert here.
Jim Stichnoth 2016/01/22 19:02:17 Done.
110 return RegMIPS32::getRegName(RegNum);
111 });
112 } 110 }
113 111
114 void TargetMIPS32::translateO2() { 112 void TargetMIPS32::translateO2() {
115 TimerMarker T(TimerStack::TT_O2, Func); 113 TimerMarker T(TimerStack::TT_O2, Func);
116 114
117 // TODO(stichnot): share passes with X86? 115 // TODO(stichnot): share passes with X86?
118 // https://code.google.com/p/nativeclient/issues/detail?id=4094 116 // https://code.google.com/p/nativeclient/issues/detail?id=4094
119 genTargetHelperCalls(); 117 genTargetHelperCalls();
120 118
121 // Merge Alloca instructions, and lay out the stack. 119 // Merge Alloca instructions, and lay out the stack.
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1113 << "nomicromips\n"; 1111 << "nomicromips\n";
1114 Str << "\t.set\t" 1112 Str << "\t.set\t"
1115 << "nomips16\n"; 1113 << "nomips16\n";
1116 } 1114 }
1117 1115
1118 llvm::SmallBitVector TargetMIPS32::TypeToRegisterSet[IceType_NUM]; 1116 llvm::SmallBitVector TargetMIPS32::TypeToRegisterSet[IceType_NUM];
1119 llvm::SmallBitVector TargetMIPS32::RegisterAliases[RegMIPS32::Reg_NUM]; 1117 llvm::SmallBitVector TargetMIPS32::RegisterAliases[RegMIPS32::Reg_NUM];
1120 1118
1121 } // end of namespace MIPS32 1119 } // end of namespace MIPS32
1122 } // end of namespace Ice 1120 } // end of namespace Ice
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