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1 // Copyright 2012 the V8 project authors. All rights reserved. | 1 // Copyright 2012 the V8 project authors. All rights reserved. |
2 // Use of this source code is governed by a BSD-style license that can be | 2 // Use of this source code is governed by a BSD-style license that can be |
3 // found in the LICENSE file. | 3 // found in the LICENSE file. |
4 | 4 |
5 #ifndef V8_ARM_MACRO_ASSEMBLER_ARM_H_ | 5 #ifndef V8_ARM_MACRO_ASSEMBLER_ARM_H_ |
6 #define V8_ARM_MACRO_ASSEMBLER_ARM_H_ | 6 #define V8_ARM_MACRO_ASSEMBLER_ARM_H_ |
7 | 7 |
8 #include "src/assembler.h" | 8 #include "src/assembler.h" |
9 #include "src/bailout-reason.h" | 9 #include "src/bailout-reason.h" |
10 #include "src/frames.h" | 10 #include "src/frames.h" |
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309 SmiCheck smi_check = INLINE_SMI_CHECK, | 309 SmiCheck smi_check = INLINE_SMI_CHECK, |
310 PointersToHereCheck pointers_to_here_check_for_value = | 310 PointersToHereCheck pointers_to_here_check_for_value = |
311 kPointersToHereMaybeInteresting); | 311 kPointersToHereMaybeInteresting); |
312 | 312 |
313 // Push a handle. | 313 // Push a handle. |
314 void Push(Handle<Object> handle); | 314 void Push(Handle<Object> handle); |
315 void Push(Smi* smi) { Push(Handle<Smi>(smi, isolate())); } | 315 void Push(Smi* smi) { Push(Handle<Smi>(smi, isolate())); } |
316 | 316 |
317 // Push two registers. Pushes leftmost register first (to highest address). | 317 // Push two registers. Pushes leftmost register first (to highest address). |
318 void Push(Register src1, Register src2, Condition cond = al) { | 318 void Push(Register src1, Register src2, Condition cond = al) { |
| 319 DCHECK(!src1.is(src2)); |
319 if (src1.code() > src2.code()) { | 320 if (src1.code() > src2.code()) { |
320 stm(db_w, sp, src1.bit() | src2.bit(), cond); | 321 stm(db_w, sp, src1.bit() | src2.bit(), cond); |
321 } else { | 322 } else { |
322 str(src1, MemOperand(sp, 4, NegPreIndex), cond); | 323 str(src1, MemOperand(sp, 4, NegPreIndex), cond); |
323 str(src2, MemOperand(sp, 4, NegPreIndex), cond); | 324 str(src2, MemOperand(sp, 4, NegPreIndex), cond); |
324 } | 325 } |
325 } | 326 } |
326 | 327 |
327 // Push three registers. Pushes leftmost register first (to highest address). | 328 // Push three registers. Pushes leftmost register first (to highest address). |
328 void Push(Register src1, Register src2, Register src3, Condition cond = al) { | 329 void Push(Register src1, Register src2, Register src3, Condition cond = al) { |
| 330 DCHECK(!AreAliased(src1, src2, src3)); |
329 if (src1.code() > src2.code()) { | 331 if (src1.code() > src2.code()) { |
330 if (src2.code() > src3.code()) { | 332 if (src2.code() > src3.code()) { |
331 stm(db_w, sp, src1.bit() | src2.bit() | src3.bit(), cond); | 333 stm(db_w, sp, src1.bit() | src2.bit() | src3.bit(), cond); |
332 } else { | 334 } else { |
333 stm(db_w, sp, src1.bit() | src2.bit(), cond); | 335 stm(db_w, sp, src1.bit() | src2.bit(), cond); |
334 str(src3, MemOperand(sp, 4, NegPreIndex), cond); | 336 str(src3, MemOperand(sp, 4, NegPreIndex), cond); |
335 } | 337 } |
336 } else { | 338 } else { |
337 str(src1, MemOperand(sp, 4, NegPreIndex), cond); | 339 str(src1, MemOperand(sp, 4, NegPreIndex), cond); |
338 Push(src2, src3, cond); | 340 Push(src2, src3, cond); |
339 } | 341 } |
340 } | 342 } |
341 | 343 |
342 // Push four registers. Pushes leftmost register first (to highest address). | 344 // Push four registers. Pushes leftmost register first (to highest address). |
343 void Push(Register src1, | 345 void Push(Register src1, |
344 Register src2, | 346 Register src2, |
345 Register src3, | 347 Register src3, |
346 Register src4, | 348 Register src4, |
347 Condition cond = al) { | 349 Condition cond = al) { |
| 350 DCHECK(!AreAliased(src1, src2, src3, src4)); |
348 if (src1.code() > src2.code()) { | 351 if (src1.code() > src2.code()) { |
349 if (src2.code() > src3.code()) { | 352 if (src2.code() > src3.code()) { |
350 if (src3.code() > src4.code()) { | 353 if (src3.code() > src4.code()) { |
351 stm(db_w, | 354 stm(db_w, |
352 sp, | 355 sp, |
353 src1.bit() | src2.bit() | src3.bit() | src4.bit(), | 356 src1.bit() | src2.bit() | src3.bit() | src4.bit(), |
354 cond); | 357 cond); |
355 } else { | 358 } else { |
356 stm(db_w, sp, src1.bit() | src2.bit() | src3.bit(), cond); | 359 stm(db_w, sp, src1.bit() | src2.bit() | src3.bit(), cond); |
357 str(src4, MemOperand(sp, 4, NegPreIndex), cond); | 360 str(src4, MemOperand(sp, 4, NegPreIndex), cond); |
358 } | 361 } |
359 } else { | 362 } else { |
360 stm(db_w, sp, src1.bit() | src2.bit(), cond); | 363 stm(db_w, sp, src1.bit() | src2.bit(), cond); |
361 Push(src3, src4, cond); | 364 Push(src3, src4, cond); |
362 } | 365 } |
363 } else { | 366 } else { |
364 str(src1, MemOperand(sp, 4, NegPreIndex), cond); | 367 str(src1, MemOperand(sp, 4, NegPreIndex), cond); |
365 Push(src2, src3, src4, cond); | 368 Push(src2, src3, src4, cond); |
366 } | 369 } |
367 } | 370 } |
368 | 371 |
369 // Push five registers. Pushes leftmost register first (to highest address). | 372 // Push five registers. Pushes leftmost register first (to highest address). |
370 void Push(Register src1, Register src2, Register src3, Register src4, | 373 void Push(Register src1, Register src2, Register src3, Register src4, |
371 Register src5, Condition cond = al) { | 374 Register src5, Condition cond = al) { |
| 375 DCHECK(!AreAliased(src1, src2, src3, src4, src5)); |
372 if (src1.code() > src2.code()) { | 376 if (src1.code() > src2.code()) { |
373 if (src2.code() > src3.code()) { | 377 if (src2.code() > src3.code()) { |
374 if (src3.code() > src4.code()) { | 378 if (src3.code() > src4.code()) { |
375 if (src4.code() > src5.code()) { | 379 if (src4.code() > src5.code()) { |
376 stm(db_w, sp, | 380 stm(db_w, sp, |
377 src1.bit() | src2.bit() | src3.bit() | src4.bit() | src5.bit(), | 381 src1.bit() | src2.bit() | src3.bit() | src4.bit() | src5.bit(), |
378 cond); | 382 cond); |
379 } else { | 383 } else { |
380 stm(db_w, sp, src1.bit() | src2.bit() | src3.bit() | src4.bit(), | 384 stm(db_w, sp, src1.bit() | src2.bit() | src3.bit() | src4.bit(), |
381 cond); | 385 cond); |
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1538 #define ACCESS_MASM(masm) masm->stop(__FILE_LINE__); masm-> | 1542 #define ACCESS_MASM(masm) masm->stop(__FILE_LINE__); masm-> |
1539 #else | 1543 #else |
1540 #define ACCESS_MASM(masm) masm-> | 1544 #define ACCESS_MASM(masm) masm-> |
1541 #endif | 1545 #endif |
1542 | 1546 |
1543 | 1547 |
1544 } // namespace internal | 1548 } // namespace internal |
1545 } // namespace v8 | 1549 } // namespace v8 |
1546 | 1550 |
1547 #endif // V8_ARM_MACRO_ASSEMBLER_ARM_H_ | 1551 #endif // V8_ARM_MACRO_ASSEMBLER_ARM_H_ |
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