Add vcvt.s32.f32 instruction to the integrated ARM assembler.

src/IceAssemblerARM32.cpp

Index: src/IceAssemblerARM32.cpp
diff --git a/src/IceAssemblerARM32.cpp b/src/IceAssemblerARM32.cpp
index 8586016c9c84f98669c5e521d38ded472c52792b..742febe36085d9c6add7a6ecbfd22118cbc77eca 100644
--- a/src/IceAssemblerARM32.cpp
+++ b/src/IceAssemblerARM32.cpp
@@ -2126,7 +2126,7 @@ void AssemblerARM32::emitVFPsd(CondARM32::Cond Cond, IValueT Opcode, IValueT Sd,
 
 void AssemblerARM32::vcvtsd(const Operand *OpSd, const Operand *OpDm,
                             CondARM32::Cond Cond) {
-  constexpr const char *Vcvtsd = "vctsd";
+  constexpr const char *Vcvtsd = "vcvtsd";
   IValueT Sd = encodeSRegister(OpSd, "Sd", Vcvtsd);
   IValueT Dm = encodeDRegister(OpDm, "Dm", Vcvtsd);
   constexpr IValueT VcvtsdOpcode =
@@ -2134,6 +2134,21 @@ void AssemblerARM32::vcvtsd(const Operand *OpSd, const Operand *OpDm,
   emitVFPsd(Cond, VcvtsdOpcode, Sd, Dm);
 }
 
+void AssemblerARM32::vcvtis(const Operand *OpSd, const Operand *OpSm,
+                            CondARM32::Cond Cond) {
+  // VCVT (between floating-point and integer, Floating-point)
+  //      - ARM Section A8.8.306, encoding A1:
+  //   vcvt<c>.s32.f32 <Sd>, <Sm>
+  //
+  // cccc11101D111101dddd10101M0mmmm where cccc=Cond, ddddD=Sd, and mmmmM=Sm.
+  constexpr const char *Vcvtis = "vcvtis";
+  IValueT Sd = encodeSRegister(OpSd, "Sd", Vcvtis);
+  IValueT Sm = encodeSRegister(OpSm, "Sm", Vcvtis);
+  constexpr IValueT VcvtsiOpcode = B23 | B21 | B20 | B19 | B18 | B16 | B7 | B6;
+  constexpr IValueT S0 = 0;
+  emitVFPsss(Cond, VcvtsiOpcode, Sd, S0, Sm);
+}
+
 void AssemblerARM32::emitVFPds(CondARM32::Cond Cond, IValueT Opcode, IValueT Dd,
                                IValueT Sm) {
   assert(Dd < RegARM32::getNumDRegs());