Add vcvt.s32.f32 instruction to the integrated ARM assembler.

src/IceAssemblerARM32.h

 //===- subzero/src/IceAssemblerARM32.h - Assembler for ARM32 ----*- C++ -*-===//
 //
 // Copyright (c) 2013, the Dart project authors.  Please see the AUTHORS file
 // for details. All rights reserved. Use of this source code is governed by a
 // BSD-style license that can be found in the LICENSE file.
 //
 // Modified by the Subzero authors.
 //
 //===----------------------------------------------------------------------===//
 //
@@ skipping 310 matching lines @@
   void vcmpd(const Operand *OpDd, const Operand *OpDm, CondARM32::Cond cond);
 
   // Second argument of compare is zero (+0.0).
   void vcmpdz(const Operand *OpDd, CondARM32::Cond cond);
 
   void vcmps(const Operand *OpSd, const Operand *OpSm, CondARM32::Cond cond);
 
   // Second argument of compare is zero (+0.0).
   void vcmpsz(const Operand *OpSd, CondARM32::Cond cond);
 
+  void vcvtds(const Operand *OpDd, const Operand *OpSm, CondARM32::Cond Cond);
+
+  // vcvt<c>.S32.F32
+  void vcvtis(const Operand *OpSd, const Operand *OpSm, CondARM32::Cond Cond);
+
   void vcvtsd(const Operand *OpSd, const Operand *OpDm, CondARM32::Cond Cond);
 
-  void vcvtds(const Operand *OpDd, const Operand *OpSm, CondARM32::Cond Cond);
-
   void vdivd(const Operand *OpDd, const Operand *OpDn, const Operand *OpDm,
              CondARM32::Cond Cond);
 
   void vdivs(const Operand *OpSd, const Operand *OpSn, const Operand *OpSm,
              CondARM32::Cond Cond);
 
   void veord(const Operand *OpDd, const Operand *OpDn, const Operand *OpDm);
 
   void vldrd(const Operand *OpDd, const Operand *OpAddress,
              CondARM32::Cond Cond, const TargetInfo &TInfo);
@@ skipping 207 matching lines @@
 
   // Emit VFP instruction with 3 S registers.
   void emitVFPsss(CondARM32::Cond Cond, IValueT Opcode, IValueT Sd, IValueT Sn,
                   IValueT Sm);
 };
 
 } // end of namespace ARM32
 } // end of namespace Ice
 
 #endif // SUBZERO_SRC_ICEASSEMBLERARM32_H