Subzero. ARM32. Fixes infinite loop during address mode formation.

src/IceTargetLoweringARM32.cpp

 //===- subzero/src/IceTargetLoweringARM32.cpp - ARM32 lowering ------------===//
 //
 //                        The Subzero Code Generator
 //
 // This file is distributed under the University of Illinois Open Source
 // License. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
 ///
 /// \file
@@ skipping 4874 matching lines @@
   if (*Var == nullptr)
     return false;
   const Inst *VarAssign = VMetadata->getSingleDefinition(*Var);
   if (!VarAssign)
     return false;
   assert(!VMetadata->isMultiDef(*Var));
   if (!llvm::isa<InstAssign>(VarAssign))
     return false;
 
   Operand *SrcOp = VarAssign->getSrc(0);
+  bool Optimized = false;
   if (auto *SrcVar = llvm::dyn_cast<Variable>(SrcOp)) {
     if (!VMetadata->isMultiDef(SrcVar) ||
         // TODO: ensure SrcVar stays single-BB
         false) {
+      Optimized = true;
       *Var = SrcVar;
     } else if (auto *Const = llvm::dyn_cast<ConstantInteger32>(SrcOp)) {
       int32_t MoreOffset = Const->getValue();
       int32_t NewOffset = MoreOffset + *Offset;
       if (Utils::WouldOverflowAdd(*Offset, MoreOffset))
         return false;
       *Var = nullptr;
       *Offset += NewOffset;
+      Optimized = true;
     }
-
-    *Reason = VarAssign;
-    return true;
   }
 
-  return false;
+  if (Optimized) {
+    *Reason = VarAssign;
+  }
+
+  return Optimized;
 }
 
 bool isAddOrSub(const Inst *Inst, InstArithmetic::OpKind *Kind) {
   if (const auto *Arith = llvm::dyn_cast<InstArithmetic>(Inst)) {
     switch (Arith->getOp()) {
     default:
       return false;
     case InstArithmetic::Add:
     case InstArithmetic::Sub:
       *Kind = Arith->getOp();
@@ skipping 1572 matching lines @@
   // However, for compatibility with current NaCl LLVM, don't claim that.
   Str << ".eabi_attribute 14, 3   @ Tag_ABI_PCS_R9_use: Not used\n";
 }
 
 llvm::SmallBitVector TargetARM32::TypeToRegisterSet[IceType_NUM];
 llvm::SmallBitVector TargetARM32::RegisterAliases[RegARM32::Reg_NUM];
 llvm::SmallBitVector TargetARM32::ScratchRegs;
 
 } // end of namespace ARM32
 } // end of namespace Ice