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| 1 //===- subzero/src/IceAssemblerARM32.h - Assembler for ARM32 ----*- C++ -*-===// | 1 //===- subzero/src/IceAssemblerARM32.h - Assembler for ARM32 ----*- C++ -*-===// |
| 2 // | 2 // |
| 3 // Copyright (c) 2013, the Dart project authors. Please see the AUTHORS file | 3 // Copyright (c) 2013, the Dart project authors. Please see the AUTHORS file |
| 4 // for details. All rights reserved. Use of this source code is governed by a | 4 // for details. All rights reserved. Use of this source code is governed by a |
| 5 // BSD-style license that can be found in the LICENSE file. | 5 // BSD-style license that can be found in the LICENSE file. |
| 6 // | 6 // |
| 7 // Modified by the Subzero authors. | 7 // Modified by the Subzero authors. |
| 8 // | 8 // |
| 9 //===----------------------------------------------------------------------===// | 9 //===----------------------------------------------------------------------===// |
| 10 // | 10 // |
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| 331 void vcvtsd(const Operand *OpSd, const Operand *OpDm, CondARM32::Cond Cond); | 331 void vcvtsd(const Operand *OpSd, const Operand *OpDm, CondARM32::Cond Cond); |
| 332 | 332 |
| 333 void vcvtds(const Operand *OpDd, const Operand *OpSm, CondARM32::Cond Cond); | 333 void vcvtds(const Operand *OpDd, const Operand *OpSm, CondARM32::Cond Cond); |
| 334 | 334 |
| 335 void vdivd(const Operand *OpDd, const Operand *OpDn, const Operand *OpDm, | 335 void vdivd(const Operand *OpDd, const Operand *OpDn, const Operand *OpDm, |
| 336 CondARM32::Cond Cond); | 336 CondARM32::Cond Cond); |
| 337 | 337 |
| 338 void vdivs(const Operand *OpSd, const Operand *OpSn, const Operand *OpSm, | 338 void vdivs(const Operand *OpSd, const Operand *OpSn, const Operand *OpSm, |
| 339 CondARM32::Cond Cond); | 339 CondARM32::Cond Cond); |
| 340 | 340 |
| 341 void veord(const Operand *OpDd, const Operand *OpDn, const Operand *OpDm); |
| 342 |
| 341 void vldrd(const Operand *OpDd, const Operand *OpAddress, | 343 void vldrd(const Operand *OpDd, const Operand *OpAddress, |
| 342 CondARM32::Cond Cond, const TargetInfo &TInfo); | 344 CondARM32::Cond Cond, const TargetInfo &TInfo); |
| 343 | 345 |
| 344 void vldrd(const Operand *OpDd, const Operand *OpAddress, | 346 void vldrd(const Operand *OpDd, const Operand *OpAddress, |
| 345 CondARM32::Cond Cond, const TargetLowering *Lowering) { | 347 CondARM32::Cond Cond, const TargetLowering *Lowering) { |
| 346 const TargetInfo TInfo(Lowering); | 348 const TargetInfo TInfo(Lowering); |
| 347 vldrd(OpDd, OpAddress, Cond, TInfo); | 349 vldrd(OpDd, OpAddress, Cond, TInfo); |
| 348 } | 350 } |
| 349 | 351 |
| 350 void vldrs(const Operand *OpSd, const Operand *OpAddress, | 352 void vldrs(const Operand *OpSd, const Operand *OpAddress, |
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| 550 | 552 |
| 551 // Emit VFP instruction with 3 S registers. | 553 // Emit VFP instruction with 3 S registers. |
| 552 void emitVFPsss(CondARM32::Cond Cond, IValueT Opcode, IValueT Sd, IValueT Sn, | 554 void emitVFPsss(CondARM32::Cond Cond, IValueT Opcode, IValueT Sd, IValueT Sn, |
| 553 IValueT Sm); | 555 IValueT Sm); |
| 554 }; | 556 }; |
| 555 | 557 |
| 556 } // end of namespace ARM32 | 558 } // end of namespace ARM32 |
| 557 } // end of namespace Ice | 559 } // end of namespace Ice |
| 558 | 560 |
| 559 #endif // SUBZERO_SRC_ICEASSEMBLERARM32_H | 561 #endif // SUBZERO_SRC_ICEASSEMBLERARM32_H |
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