Add instruction veord to the integrated ARM assembler.

src/IceAssemblerARM32.cpp

 //===- subzero/src/IceAssemblerARM32.cpp - Assembler for ARM32 --*- C++ -*-===//
 //
 // Copyright (c) 2013, the Dart project authors.  Please see the AUTHORS file
 // for details. All rights reserved. Use of this source code is governed by a
 // BSD-style license that can be found in the LICENSE file.
 //
 // Modified by the Subzero authors.
 //
 //===----------------------------------------------------------------------===//
 //
@@ skipping 2170 matching lines @@
   // cccc11101D00nnnndddd101sN0M0mmmm where cccc=Cond, s=1, Ddddd=Rd, Nnnnn=Rn,
   // and Mmmmm=Rm.
   constexpr const char *Vdivd = "vdivd";
   IValueT Dd = encodeDRegister(OpDd, "Dd", Vdivd);
   IValueT Dn = encodeDRegister(OpDn, "Dn", Vdivd);
   IValueT Dm = encodeDRegister(OpDm, "Dm", Vdivd);
   constexpr IValueT VdivdOpcode = B23;
   emitVFPddd(Cond, VdivdOpcode, Dd, Dn, Dm);
 }
 
+void AssemblerARM32::veord(const Operand *OpDd, const Operand *OpDn,
+                           const Operand *OpDm) {
+  // VEOR - ARM secdtion A8.8.315, encoding A1:
+  //   veor<c> <Dd>, <Dn>, <Dm>
+  //
+  // 111100110D00nnnndddd0001N0M1mmmm where Ddddd=Dd, Nnnnn=Dn, and Mmmmm=Dm.
+  constexpr const char *Veord = "veord";
+  IValueT Dd = encodeDRegister(OpDd, "Dd", Veord);
+  IValueT Dn = encodeDRegister(OpDn, "Dn", Veord);
+  IValueT Dm = encodeDRegister(OpDm, "Dm", Veord);
+  AssemblerBuffer::EnsureCapacity ensured(&Buffer);
+  const IValueT Encoding =
+      B25 | B24 | B8 | B4 |
+      (encodeCondition(CondARM32::Cond::kNone) << kConditionShift) |
+      (getYInRegYXXXX(Dd) << 22) | (getXXXXInRegYXXXX(Dn) << 16) |
+      (getXXXXInRegYXXXX(Dd) << 12) | (getYInRegYXXXX(Dn) << 7) |
+      (getYInRegYXXXX(Dm) << 5) | getXXXXInRegYXXXX(Dm);
+  emitInst(Encoding);
+}
+
 void AssemblerARM32::vldrd(const Operand *OpDd, const Operand *OpAddress,
                            CondARM32::Cond Cond, const TargetInfo &TInfo) {
   // VLDR - ARM section A8.8.333, encoding A1.
   //   vldr<c> <Dd>, [<Rn>{, #+/-<imm>}]
   //
   // cccc1101UD01nnnndddd1011iiiiiiii where cccc=Cond, nnnn=Rn, Ddddd=Rd,
   // iiiiiiii=abs(Opcode), and U=1 if Opcode>=0,
   constexpr const char *Vldrd = "vldrd";
   IValueT Dd = encodeDRegister(OpDd, "Dd", Vldrd);
   assert(CondARM32::isDefined(Cond));
@@ skipping 174 matching lines @@
   //
   // cccc11010D101101dddd1010iiiiiiii where cccc=Cond, ddddD=BaseReg, and
   // iiiiiiii=NumConsecRegs.
   constexpr IValueT VpushOpcode =
       B27 | B26 | B24 | B21 | B19 | B18 | B16 | B11 | B9;
   emitVStackOp(Cond, VpushOpcode, OpBaseReg, NumConsecRegs);
 }
 
 } // end of namespace ARM32
 } // end of namespace Ice