Add vstr{s,d} to the integrated ARM assembler.

src/IceAssemblerARM32.cpp

 //===- subzero/src/IceAssemblerARM32.cpp - Assembler for ARM32 --*- C++ -*-===//
 //
 // Copyright (c) 2013, the Dart project authors.  Please see the AUTHORS file
 // for details. All rights reserved. Use of this source code is governed by a
 // BSD-style license that can be found in the LICENSE file.
 //
 // Modified by the Subzero authors.
 //
 //===----------------------------------------------------------------------===//
 //
@@ skipping 2199 matching lines @@
   // cccc11100D10nnnndddd101sN0M0mmmm where cccc=Cond, s=1, Ddddd=Rd, Nnnnn=Rn,
   // and Mmmmm=Rm.
   constexpr const char *Vmuld = "vmuld";
   IValueT Dd = encodeDRegister(OpDd, "Dd", Vmuld);
   IValueT Dn = encodeDRegister(OpDn, "Dn", Vmuld);
   IValueT Dm = encodeDRegister(OpDm, "Dm", Vmuld);
   constexpr IValueT VmuldOpcode = B21;
   emitVFPddd(Cond, VmuldOpcode, Dd, Dn, Dm);
 }
 
+void AssemblerARM32::vstrd(const Operand *OpDd, const Operand *OpAddress,
+                           CondARM32::Cond Cond, const TargetInfo &TInfo) {
+  // VSTR - ARM section A8.8.413, encoding A1:
+  //   vstr<c> <Dd>, [<Rn>{, #+/-<imm>}]
+  //
+  // cccc1101UD00nnnndddd1011iiiiiiii where cccc=Cond, nnnn=Rn, Ddddd=Rd,
+  // iiiiiiii=abs(Opcode), and U=1 if Opcode>=0,
+  constexpr const char *Vstrd = "vstrd";
+  IValueT Dd = encodeDRegister(OpDd, "Dd", Vstrd);
+  assert(CondARM32::isDefined(Cond));
+  IValueT Address;
+  if (encodeAddress(OpAddress, Address, TInfo) != EncodedAsImmRegOffset)
+    assert(false);
+  AssemblerBuffer::EnsureCapacity ensured(&Buffer);
+  IValueT Encoding = B27 | B26 | B24 | B11 | B9 | B8 |
+                     (encodeCondition(Cond) << kConditionShift) |
+                     (getYInRegYXXXX(Dd) << 22) |
+                     (getXXXXInRegYXXXX(Dd) << 12) | Address;
+  emitInst(Encoding);
+}
+
+void AssemblerARM32::vstrs(const Operand *OpSd, const Operand *OpAddress,
+                           CondARM32::Cond Cond, const TargetInfo &TInfo) {
+  // VSTR - ARM section A8.8.413, encoding A2:
+  //   vstr<c> <Sd>, [<Rn>{, #+/-<imm>]]
+  //
+  // cccc1101UD01nnnndddd1010iiiiiiii where cccc=Cond, nnnn=Rn, ddddD=Sd,
+  // iiiiiiii=abs(Opcode), and U=1 if Opcode >= 0;
+  constexpr const char *Vstrs = "vstrs";
+  IValueT Sd = encodeSRegister(OpSd, "Sd", Vstrs);
+  assert(CondARM32::isDefined(Cond));
+  IValueT Address;
+  if (encodeAddress(OpAddress, Address, TInfo) != EncodedAsImmRegOffset)
+    assert(false);
+  AssemblerBuffer::EnsureCapacity ensured(&Buffer);
+  IValueT Encoding =
+      B27 | B26 | B24 | B11 | B9 | (encodeCondition(Cond) << kConditionShift) |
+      (getYInRegXXXXY(Sd) << 22) | (getXXXXInRegXXXXY(Sd) << 12) | Address;
+  emitInst(Encoding);
+}
+
 void AssemblerARM32::vsubs(const Operand *OpSd, const Operand *OpSn,
                            const Operand *OpSm, CondARM32::Cond Cond) {
   // VSUB (floating-point) - ARM section A8.8.415, encoding A2:
   //   vsub<c>.f32 <Sd>, <Sn>, <Sm>
   //
   // cccc11100D11nnnndddd101sN1M0mmmm where cccc=Cond, s=0, ddddD=Rd, nnnnN=Rn,
   // and mmmmM=Rm.
   constexpr const char *Vsubs = "vsubs";
   IValueT Sd = encodeSRegister(OpSd, "Sd", Vsubs);
   IValueT Sn = encodeSRegister(OpSn, "Sn", Vsubs);
@@ skipping 59 matching lines @@
   //
   // cccc11010D101101dddd1010iiiiiiii where cccc=Cond, ddddD=BaseReg, and
   // iiiiiiii=NumConsecRegs.
   constexpr IValueT VpushOpcode =
       B27 | B26 | B24 | B21 | B19 | B18 | B16 | B11 | B9;
   emitVStackOp(Cond, VpushOpcode, OpBaseReg, NumConsecRegs);
 }
 
 } // end of namespace ARM32
 } // end of namespace Ice