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| 1 // Copyright (c) 2013, the Dart project authors. Please see the AUTHORS file | 1 // Copyright (c) 2013, the Dart project authors. Please see the AUTHORS file |
| 2 // for details. All rights reserved. Use of this source code is governed by a | 2 // for details. All rights reserved. Use of this source code is governed by a |
| 3 // BSD-style license that can be found in the LICENSE file. | 3 // BSD-style license that can be found in the LICENSE file. |
| 4 | 4 |
| 5 #ifndef VM_CONSTANTS_MIPS_H_ | 5 #ifndef VM_CONSTANTS_MIPS_H_ |
| 6 #define VM_CONSTANTS_MIPS_H_ | 6 #define VM_CONSTANTS_MIPS_H_ |
| 7 | 7 |
| 8 #include "platform/assert.h" | 8 #include "platform/assert.h" |
| 9 | 9 |
| 10 namespace dart { | 10 namespace dart { |
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| 122 F26 = 26, | 122 F26 = 26, |
| 123 F27 = 27, | 123 F27 = 27, |
| 124 F28 = 28, | 124 F28 = 28, |
| 125 F29 = 29, | 125 F29 = 29, |
| 126 F30 = 30, | 126 F30 = 30, |
| 127 F31 = 31, | 127 F31 = 31, |
| 128 kNumberOfFRegisters = 32, | 128 kNumberOfFRegisters = 32, |
| 129 kNoFRegister = -1, | 129 kNoFRegister = -1, |
| 130 }; | 130 }; |
| 131 | 131 |
| 132 // The double precision floating point registers are concatenated pairs of the |
| 133 // single precision registers, e.g. D0 is F1:F0, D1 is F3:F2, etc.. We only |
| 134 // tell the architecture generic code about the double precision registers, then |
| 135 // convert to the single precision registers when needed in the mips-specific |
| 136 // code. |
| 137 enum DRegister { |
| 138 D0 = 0, |
| 139 D1 = 1, |
| 140 D2 = 2, |
| 141 D3 = 3, |
| 142 D4 = 4, |
| 143 D5 = 5, |
| 144 D6 = 6, |
| 145 D7 = 7, |
| 146 D8 = 8, |
| 147 D9 = 9, |
| 148 D10 = 10, |
| 149 D11 = 11, |
| 150 D12 = 12, |
| 151 D13 = 13, |
| 152 D14 = 14, |
| 153 D15 = 15, |
| 154 D16 = 16, |
| 155 kNumberOfDRegisters = 16, |
| 156 kNoDRegister = -1, |
| 157 }; |
| 132 | 158 |
| 133 // Architecture independent aliases. | 159 // Architecture independent aliases. |
| 134 typedef FRegister FpuRegister; | 160 typedef DRegister FpuRegister; |
| 135 const FpuRegister FpuTMP = F0; | 161 const FpuRegister FpuTMP = D0; |
| 136 const int kNumberOfFpuRegisters = kNumberOfFRegisters; | 162 const int kNumberOfFpuRegisters = kNumberOfDRegisters; |
| 137 const FpuRegister kNoFpuRegister = kNoFRegister; | 163 const FpuRegister kNoFpuRegister = kNoDRegister; |
| 138 | 164 |
| 139 | 165 |
| 140 // Register aliases. | 166 // Register aliases. |
| 141 const Register TMP1 = AT; // Used as scratch register by assembler. | 167 const Register TMP1 = AT; // Used as scratch register by assembler. |
| 142 const Register TMP = TMP1; // Arch independent flow graph compiler needs a | 168 const Register TMP = TMP1; // Arch independent flow graph compiler needs a |
| 143 // Register called TMP. | 169 // Register called TMP. |
| 144 const Register CTX = S6; // Caches current context in generated code. | 170 const Register CTX = S6; // Caches current context in generated code. |
| 145 const Register PP = S7; // Caches object pool pointer in generated code. | 171 const Register PP = S7; // Caches object pool pointer in generated code. |
| 146 const Register SPREG = SP; // Stack pointer register. | 172 const Register SPREG = SP; // Stack pointer register. |
| 147 const Register FPREG = FP; // Frame pointer register. | 173 const Register FPREG = FP; // Frame pointer register. |
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| 565 #endif // defined(DEBUG) | 591 #endif // defined(DEBUG) |
| 566 | 592 |
| 567 private: | 593 private: |
| 568 DISALLOW_ALLOCATION(); | 594 DISALLOW_ALLOCATION(); |
| 569 DISALLOW_IMPLICIT_CONSTRUCTORS(Instr); | 595 DISALLOW_IMPLICIT_CONSTRUCTORS(Instr); |
| 570 }; | 596 }; |
| 571 | 597 |
| 572 } // namespace dart | 598 } // namespace dart |
| 573 | 599 |
| 574 #endif // VM_CONSTANTS_MIPS_H_ | 600 #endif // VM_CONSTANTS_MIPS_H_ |
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