Enables optimization on MIPS

runtime/vm/assembler_mips.h

 // Copyright (c) 2013, the Dart project authors.  Please see the AUTHORS file
 // for details. All rights reserved. Use of this source code is governed by a
 // BSD-style license that can be found in the LICENSE file.
 
 #ifndef VM_ASSEMBLER_MIPS_H_
 #define VM_ASSEMBLER_MIPS_H_
 
 #ifndef VM_ASSEMBLER_H_
 #error Do not include assembler_mips.h directly; use assembler.h instead.
 #endif
@@ skipping 212 matching lines @@
     ASSERT(delay_slot_available_);
     ASSERT(buffer_.Load<int32_t>(buffer_.GetPosition() - sizeof(int32_t)) ==
         Instr::kNopInstruction);
     buffer_.Remit<int32_t>();
     delay_slot_available_ = false;
     in_delay_slot_ = true;
     return this;
   }
 
   // CPU instructions in alphabetical order.
-  void addd(FRegister fd, FRegister fs, FRegister ft) {
-    ASSERT(EvenFPURegister(fd));
-    ASSERT(EvenFPURegister(fs));
-    ASSERT(EvenFPURegister(ft));
+  void addd(DRegister dd, DRegister ds, DRegister dt) {
+    // DRegisters start at the even FRegisters.
+    FRegister fd = static_cast<FRegister>(dd * 2);
+    FRegister fs = static_cast<FRegister>(ds * 2);
+    FRegister ft = static_cast<FRegister>(dt * 2);
     EmitFpuRType(COP1, FMT_D, ft, fs, fd, COP1_ADD);
   }
 
   void addiu(Register rt, Register rs, const Immediate& imm) {
     ASSERT(Utils::IsInt(kImmBits, imm.value()));
     const uint16_t imm_value = static_cast<uint16_t>(imm.value());
     EmitIType(ADDIU, rs, rt, imm_value);
   }
 
   void addu(Register rd, Register rs, Register rt) {
@@ skipping 124 matching lines @@
   }
 
   void break_(int32_t code) {
     ASSERT(Utils::IsUint(20, code));
     Emit(SPECIAL << kOpcodeShift |
          code << kBreakCodeShift |
          BREAK << kFunctionShift);
   }
 
   // FPU compare, always false.
-  void cfd(FRegister fs, FRegister ft) {
-    ASSERT(EvenFPURegister(fs));
-    ASSERT(EvenFPURegister(ft));
+  void cfd(DRegister ds, DRegister dt) {
+    FRegister fs = static_cast<FRegister>(ds * 2);
+    FRegister ft = static_cast<FRegister>(dt * 2);
     EmitFpuRType(COP1, FMT_D, ft, fs, F0, COP1_C_F);
   }
 
   // FPU compare, true if unordered, i.e. one is NaN.
-  void cund(FRegister fs, FRegister ft) {
-    ASSERT(EvenFPURegister(fs));
-    ASSERT(EvenFPURegister(ft));
+  void cund(DRegister ds, DRegister dt) {
+    FRegister fs = static_cast<FRegister>(ds * 2);
+    FRegister ft = static_cast<FRegister>(dt * 2);
     EmitFpuRType(COP1, FMT_D, ft, fs, F0, COP1_C_UN);
   }
 
   // FPU compare, true if equal.
-  void ceqd(FRegister fs, FRegister ft) {
-    ASSERT(EvenFPURegister(fs));
-    ASSERT(EvenFPURegister(ft));
+  void ceqd(DRegister ds, DRegister dt) {
+    FRegister fs = static_cast<FRegister>(ds * 2);
+    FRegister ft = static_cast<FRegister>(dt * 2);
     EmitFpuRType(COP1, FMT_D, ft, fs, F0, COP1_C_EQ);
   }
 
   // FPU compare, true if unordered or equal.
-  void cueqd(FRegister fs, FRegister ft) {
-    ASSERT(EvenFPURegister(fs));
-    ASSERT(EvenFPURegister(ft));
+  void cueqd(DRegister ds, DRegister dt) {
+    FRegister fs = static_cast<FRegister>(ds * 2);
+    FRegister ft = static_cast<FRegister>(dt * 2);
     EmitFpuRType(COP1, FMT_D, ft, fs, F0, COP1_C_UEQ);
   }
 
   // FPU compare, true if less than.
-  void coltd(FRegister fs, FRegister ft) {
-    ASSERT(EvenFPURegister(fs));
-    ASSERT(EvenFPURegister(ft));
+  void coltd(DRegister ds, DRegister dt) {
+    FRegister fs = static_cast<FRegister>(ds * 2);
+    FRegister ft = static_cast<FRegister>(dt * 2);
     EmitFpuRType(COP1, FMT_D, ft, fs, F0, COP1_C_OLT);
   }
 
   // FPU compare, true if unordered or less than.
-  void cultd(FRegister fs, FRegister ft) {
-    ASSERT(EvenFPURegister(fs));
-    ASSERT(EvenFPURegister(ft));
+  void cultd(DRegister ds, DRegister dt) {
+    FRegister fs = static_cast<FRegister>(ds * 2);
+    FRegister ft = static_cast<FRegister>(dt * 2);
     EmitFpuRType(COP1, FMT_D, ft, fs, F0, COP1_C_ULT);
   }
 
   // FPU compare, true if less or equal.
-  void coled(FRegister fs, FRegister ft) {
-    ASSERT(EvenFPURegister(fs));
-    ASSERT(EvenFPURegister(ft));
+  void coled(DRegister ds, DRegister dt) {
+    FRegister fs = static_cast<FRegister>(ds * 2);
+    FRegister ft = static_cast<FRegister>(dt * 2);
     EmitFpuRType(COP1, FMT_D, ft, fs, F0, COP1_C_OLE);
   }
 
   // FPU compare, true if unordered or less or equal.
-  void culed(FRegister fs, FRegister ft) {
-    ASSERT(EvenFPURegister(fs));
-    ASSERT(EvenFPURegister(ft));
+  void culed(DRegister ds, DRegister dt) {
+    FRegister fs = static_cast<FRegister>(ds * 2);
+    FRegister ft = static_cast<FRegister>(dt * 2);
     EmitFpuRType(COP1, FMT_D, ft, fs, F0, COP1_C_ULE);
   }
 
   void clo(Register rd, Register rs) {
     EmitRType(SPECIAL2, rs, rd, rd, 0, CLO);
   }
 
   void clz(Register rd, Register rs) {
     EmitRType(SPECIAL2, rs, rd, rd, 0, CLZ);
   }
 
   // Converts a 32-bit signed int in fs to a double in fd.
-  void cvtdw(FRegister fd, FRegister fs) {
-    ASSERT(EvenFPURegister(fd));
+  void cvtdw(DRegister dd, FRegister fs) {
+    FRegister fd = static_cast<FRegister>(dd * 2);
     EmitFpuRType(COP1, FMT_W, F0, fs, fd, COP1_CVT_D);
   }
 
   // Converts a 64-bit signed int in fs to a double in fd.
-  void cvtdl(FRegister fd, FRegister fs) {
-    ASSERT(EvenFPURegister(fs));
-    ASSERT(EvenFPURegister(fd));
+  void cvtdl(DRegister dd, DRegister ds) {
+    FRegister fs = static_cast<FRegister>(ds * 2);
+    FRegister fd = static_cast<FRegister>(dd * 2);
     EmitFpuRType(COP1, FMT_L, F0, fs, fd, COP1_CVT_D);
   }
 
-  void cvtwd(FRegister fd, FRegister fs) {
-    ASSERT(EvenFPURegister(fs));
-    ASSERT(EvenFPURegister(fd));
+  void cvtwd(FRegister fd, DRegister ds) {
+    FRegister fs = static_cast<FRegister>(ds * 2);
     EmitFpuRType(COP1, FMT_D, F0, fs, fd, COP1_CVT_W);
   }
 
   void div(Register rs, Register rt) {
     EmitRType(SPECIAL, rs, rt, R0, 0, DIV);
   }
 
-  void divd(FRegister fd, FRegister fs, FRegister ft) {
-    ASSERT(EvenFPURegister(fd));
-    ASSERT(EvenFPURegister(fs));
-    ASSERT(EvenFPURegister(ft));
+  void divd(DRegister dd, DRegister ds, DRegister dt) {
+    FRegister fd = static_cast<FRegister>(dd * 2);
+    FRegister fs = static_cast<FRegister>(ds * 2);
+    FRegister ft = static_cast<FRegister>(dt * 2);
     EmitFpuRType(COP1, FMT_D, ft, fs, fd, COP1_DIV);
   }
 
   void divu(Register rs, Register rt) {
     EmitRType(SPECIAL, rs, rt, R0, 0, DIVU);
   }
 
   void jalr(Register rs, Register rd = RA) {
     ASSERT(rs != rd);
     ASSERT(!in_delay_slot_);  // Jump within a delay slot is not supported.
     EmitRType(SPECIAL, rs, R0, rd, 0, JALR);
     EmitBranchDelayNop();
   }
 
   void jr(Register rs) {
     ASSERT(!in_delay_slot_);  // Jump within a delay slot is not supported.
     EmitRType(SPECIAL, rs, R0, R0, 0, JR);
     EmitBranchDelayNop();
   }
 
   void lb(Register rt, const Address& addr) {
     EmitLoadStore(LB, rt, addr);
   }
 
   void lbu(Register rt, const Address& addr) {
     EmitLoadStore(LBU, rt, addr);
   }
 
-  void ldc1(FRegister ft, const Address& addr) {
-    ASSERT(EvenFPURegister(ft));
+  void ldc1(DRegister dt, const Address& addr) {
+    FRegister ft = static_cast<FRegister>(dt * 2);
     EmitFpuLoadStore(LDC1, ft, addr);
   }
 
   void lh(Register rt, const Address& addr) {
     EmitLoadStore(LH, rt, addr);
   }
 
   void lhu(Register rt, const Address& addr) {
     EmitLoadStore(LHU, rt, addr);
   }
@@ skipping 24 matching lines @@
   }
 
   void mflo(Register rd) {
     EmitRType(SPECIAL, R0, R0, rd, 0, MFLO);
   }
 
   void mov(Register rd, Register rs) {
     or_(rd, rs, ZR);
   }
 
-  void movd(FRegister fd, FRegister fs) {
-    ASSERT(EvenFPURegister(fd));
-    ASSERT(EvenFPURegister(fs));
+  void movd(DRegister dd, DRegister ds) {
+    FRegister fd = static_cast<FRegister>(dd * 2);
+    FRegister fs = static_cast<FRegister>(ds * 2);
     EmitFpuRType(COP1, FMT_D, F0, fs, fd, COP1_MOV);
   }
 
   void movn(Register rd, Register rs, Register rt) {
     EmitRType(SPECIAL, rs, rt, rd, 0, MOVN);
   }
 
   void movz(Register rd, Register rs, Register rt) {
     EmitRType(SPECIAL, rs, rt, rd, 0, MOVZ);
   }
 
   void movs(FRegister fd, FRegister fs) {
     EmitFpuRType(COP1, FMT_S, F0, fs, fd, COP1_MOV);
   }
 
   void mtc1(Register rt, FRegister fs) {
     Emit(COP1 << kOpcodeShift |
          COP1_MT << kCop1SubShift |
          rt << kRtShift |
          fs << kFsShift);
   }
 
-  void muld(FRegister fd, FRegister fs, FRegister ft) {
-    ASSERT(EvenFPURegister(fd));
-    ASSERT(EvenFPURegister(fs));
-    ASSERT(EvenFPURegister(ft));
+  void muld(DRegister dd, DRegister ds, DRegister dt) {
+    FRegister fd = static_cast<FRegister>(dd * 2);
+    FRegister fs = static_cast<FRegister>(ds * 2);
+    FRegister ft = static_cast<FRegister>(dt * 2);
     EmitFpuRType(COP1, FMT_D, ft, fs, fd, COP1_MUL);
   }
 
   void mult(Register rs, Register rt) {
     EmitRType(SPECIAL, rs, rt, R0, 0, MULT);
   }
 
   void multu(Register rs, Register rt) {
     EmitRType(SPECIAL, rs, rt, R0, 0, MULTU);
   }
@@ skipping 13 matching lines @@
   void ori(Register rt, Register rs, const Immediate& imm) {
     ASSERT(Utils::IsUint(kImmBits, imm.value()));
     uint16_t imm_value = static_cast<uint16_t>(imm.value());
     EmitIType(ORI, rs, rt, imm_value);
   }
 
   void sb(Register rt, const Address& addr) {
     EmitLoadStore(SB, rt, addr);
   }
 
-  void sdc1(FRegister ft, const Address& addr) {
-    ASSERT(EvenFPURegister(ft));
+  void sdc1(DRegister dt, const Address& addr) {
+    FRegister ft = static_cast<FRegister>(dt * 2);
     EmitFpuLoadStore(SDC1, ft, addr);
   }
 
   void sh(Register rt, const Address& addr) {
     EmitLoadStore(SH, rt, addr);
   }
 
   void sll(Register rd, Register rt, int sa) {
     EmitRType(SPECIAL, R0, rt, rd, sa, SLL);
   }
 
   void sllv(Register rd, Register rt, Register rs) {
     EmitRType(SPECIAL, rs, rt, rd, 0, SLLV);
   }
 
   void slt(Register rd, Register rs, Register rt) {
     EmitRType(SPECIAL, rs, rt, rd, 0, SLT);
   }
 
+  void slti(Register rt, Register rs, const Immediate& imm) {
+    ASSERT(Utils::IsInt(kImmBits, imm.value()));
+    int16_t imm_value = static_cast<int16_t>(imm.value());
+    EmitIType(SLTI, rs, rt, imm_value);
+  }
+
+  void sltiu(Register rt, Register rs, const Immediate& imm) {
+    ASSERT(Utils::IsUint(kImmBits, imm.value()));
+    uint16_t imm_value = static_cast<uint16_t>(imm.value());
+    EmitIType(SLTIU, rs, rt, imm_value);
+  }
+
   void sltu(Register rd, Register rs, Register rt) {
     EmitRType(SPECIAL, rs, rt, rd, 0, SLTU);
   }
 
-  void sqrtd(FRegister fd, FRegister fs) {
-    ASSERT(EvenFPURegister(fd));
-    ASSERT(EvenFPURegister(fs));
+  void sqrtd(DRegister dd, DRegister ds) {
+    FRegister fd = static_cast<FRegister>(dd * 2);
+    FRegister fs = static_cast<FRegister>(ds * 2);
     EmitFpuRType(COP1, FMT_D, F0, fs, fd, COP1_SQRT);
   }
 
   void sra(Register rd, Register rt, int sa) {
     EmitRType(SPECIAL, R0, rt, rd, sa, SRA);
   }
 
   void srav(Register rd, Register rt, Register rs) {
     EmitRType(SPECIAL, rs, rt, rd, 0, SRAV);
   }
 
   void srl(Register rd, Register rt, int sa) {
     EmitRType(SPECIAL, R0, rt, rd, sa, SRL);
   }
 
   void srlv(Register rd, Register rt, Register rs) {
     EmitRType(SPECIAL, rs, rt, rd, 0, SRLV);
   }
 
-  void subd(FRegister fd, FRegister fs, FRegister ft) {
-    ASSERT(EvenFPURegister(fd));
-    ASSERT(EvenFPURegister(fs));
-    ASSERT(EvenFPURegister(ft));
+  void subd(DRegister dd, DRegister ds, DRegister dt) {
+    FRegister fd = static_cast<FRegister>(dd * 2);
+    FRegister fs = static_cast<FRegister>(ds * 2);
+    FRegister ft = static_cast<FRegister>(dt * 2);
     EmitFpuRType(COP1, FMT_D, ft, fs, fd, COP1_SUB);
   }
 
   void subu(Register rd, Register rs, Register rt) {
     EmitRType(SPECIAL, rs, rt, rd, 0, SUBU);
   }
 
   void sw(Register rt, const Address& addr) {
     EmitLoadStore(SW, rt, addr);
   }
@@ skipping 85 matching lines @@
     if (Utils::IsInt(kImmBits, value)) {
       addiu(rd, ZR, Immediate(value));
     } else {
       const uint16_t low = Utils::Low16Bits(value);
       const uint16_t high = Utils::High16Bits(value);
       lui(rd, Immediate(high));
       ori(rd, rd, Immediate(low));
     }
   }
 
-  void LoadImmediate(FRegister rd, double value) {
-    ASSERT(EvenFPURegister(rd));
+  void LoadImmediate(DRegister rd, double value) {
+    FRegister frd = static_cast<FRegister>(rd * 2);
     const int64_t ival = bit_cast<uint64_t, double>(value);
     const int32_t low = Utils::Low32Bits(ival);
     const int32_t high = Utils::High32Bits(ival);
     if (low != 0) {
       LoadImmediate(TMP1, low);
-      mtc1(TMP1, rd);
+      mtc1(TMP1, frd);
     } else {
-      mtc1(ZR, rd);
+      mtc1(ZR, frd);
     }
 
     if (high != 0) {
       LoadImmediate(TMP1, high);
-      mtc1(TMP1, static_cast<FRegister>(rd + 1));
+      mtc1(TMP1, static_cast<FRegister>(frd + 1));
     } else {
-      mtc1(ZR, static_cast<FRegister>(rd + 1));
+      mtc1(ZR, static_cast<FRegister>(frd + 1));
     }
   }
 
   void LoadImmediate(FRegister rd, float value) {
     const int32_t ival = bit_cast<int32_t, float>(value);
     if (ival == 0) {
       mtc1(ZR, rd);
     } else {
       LoadImmediate(TMP1, ival);
       mtc1(TMP1, rd);
@@ skipping 56 matching lines @@
     LoadImmediate(CMPRES, value);
     BranchUnsignedGreater(rd, CMPRES, l);
   }
 
   void BranchSignedGreaterEqual(Register rd, Register rs, Label* l) {
     slt(CMPRES, rd, rs);  // CMPRES = rd < rs ? 1 : 0.
     beq(CMPRES, ZR, l);  // If CMPRES = 0, then rd >= rs.
   }
 
   void BranchSignedGreaterEqual(Register rd, int32_t value, Label* l) {
-    LoadImmediate(CMPRES, value);
-    BranchSignedGreaterEqual(rd, CMPRES, l);
+    if (Utils::IsInt(kImmBits, value)) {
+      slti(CMPRES, rd, Immediate(value));
+      beq(CMPRES, ZR, l);
+    } else {
+      LoadImmediate(CMPRES, value);
+      BranchSignedGreaterEqual(rd, CMPRES, l);
+    }
   }
 
   void BranchUnsignedGreaterEqual(Register rd, Register rs, Label* l) {
     sltu(CMPRES, rd, rs);  // CMPRES = rd < rs ? 1 : 0.
     beq(CMPRES, ZR, l);
   }
 
   void BranchUnsignedGreaterEqual(Register rd, int32_t value, Label* l) {
-    LoadImmediate(CMPRES, value);
-    BranchUnsignedGreaterEqual(rd, CMPRES, l);
+    if (Utils::IsUint(kImmBits, value)) {
+      sltiu(CMPRES, rd, Immediate(value));
+      beq(CMPRES, ZR, l);
+    } else {
+      LoadImmediate(CMPRES, value);
+      BranchUnsignedGreaterEqual(rd, CMPRES, l);
+    }
   }
 
   void BranchSignedLess(Register rd, Register rs, Label* l) {
     BranchSignedGreater(rs, rd, l);
   }
 
   void BranchSignedLess(Register rd, int32_t value, Label* l) {
-    LoadImmediate(CMPRES, value);
-    BranchSignedGreater(CMPRES, rd, l);
+    if (Utils::IsInt(kImmBits, value)) {
+      slti(CMPRES, rd, Immediate(value));
+      bne(CMPRES, ZR, l);
+    } else {
+      LoadImmediate(CMPRES, value);
+      BranchSignedGreater(CMPRES, rd, l);
+    }
   }
 
   void BranchUnsignedLess(Register rd, Register rs, Label* l) {
     BranchUnsignedGreater(rs, rd, l);
   }
 
   void BranchUnsignedLess(Register rd, int32_t value, Label* l) {
-    LoadImmediate(CMPRES, value);
-    BranchUnsignedGreater(CMPRES, rd, l);
+    if (Utils::IsUint(kImmBits, value)) {
+      sltiu(CMPRES, rd, Immediate(value));
+      bne(CMPRES, ZR, l);
+    } else {
+      LoadImmediate(CMPRES, value);
+      BranchUnsignedGreater(CMPRES, rd, l);
+    }
   }
 
   void BranchSignedLessEqual(Register rd, Register rs, Label* l) {
     BranchSignedGreaterEqual(rs, rd, l);
   }
 
   void BranchSignedLessEqual(Register rd, int32_t value, Label* l) {
     LoadImmediate(CMPRES, value);
     BranchSignedGreaterEqual(CMPRES, rd, l);
   }
@@ skipping 34 matching lines @@
   // Create a frame for calling into runtime that preserves all volatile
   // registers.  Frame's SP is guaranteed to be correctly aligned and
   // frame_space bytes are reserved under it.
   void EnterCallRuntimeFrame(intptr_t frame_space);
   void LeaveCallRuntimeFrame();
 
   void LoadWordFromPoolOffset(Register rd, int32_t offset);
   void LoadObject(Register rd, const Object& object);
   void PushObject(const Object& object);
 
-  // Sets register rd to zero if the object is equal to register rn,
-  // sets it to non-zero otherwise.
-  void CompareObject(Register rd, Register rn, const Object& object);
+  // Compares rn with the object. Returns results in rd1 and rd2.
+  // rd1 is 1 if rn < object. rd2 is 1 if object < rn. Since both cannot be
+  // 1, rd1 == rd2 (== 0) iff rn == object.
+  void CompareObject(Register rd1, Register rd2,
+                     Register rn, const Object& object);
 
   void LoadClassId(Register result, Register object);
   void LoadClassById(Register result, Register class_id);
   void LoadClass(Register result, Register object);
 
   void StoreIntoObject(Register object,  // Object we are storing into.
                        const Address& dest,  // Where we are storing into.
                        Register value,  // Value we are storing.
                        bool can_value_be_smi = true);
 
@@ skipping 33 matching lines @@
 
    private:
     intptr_t pc_offset_;
     const String& comment_;
 
     DISALLOW_COPY_AND_ASSIGN(CodeComment);
   };
 
   GrowableArray<CodeComment*> comments_;
 
-  bool EvenFPURegister(FRegister reg) {
-    return (static_cast<int>(reg) & 1) == 0;
-  }
-
   void Emit(int32_t value) {
     // Emitting an instruction clears the delay slot state.
     in_delay_slot_ = false;
     delay_slot_available_ = false;
     AssemblerBuffer::EnsureCapacity ensured(&buffer_);
     buffer_.Emit<int32_t>(value);
   }
 
   // Encode CPU instructions according to the types specified in
   // Figures 4-1, 4-2 and 4-3 in VolI-A.
@@ skipping 131 matching lines @@
                                   Register value,
                                   Label* no_update);
 
   DISALLOW_ALLOCATION();
   DISALLOW_COPY_AND_ASSIGN(Assembler);
 };
 
 }  // namespace dart
 
 #endif  // VM_ASSEMBLER_MIPS_H_