Add vdlr{s,d} to the integrated ARM assembler.

tests_lit/assembler/arm32/vldr.ll

Index: tests_lit/assembler/arm32/vldr.ll
diff --git a/tests_lit/assembler/arm32/vldr.ll b/tests_lit/assembler/arm32/vldr.ll
new file mode 100644
index 0000000000000000000000000000000000000000..0bdf5bd2e95435c11506d56f772c749c0929a898
--- /dev/null
+++ b/tests_lit/assembler/arm32/vldr.ll
@@ -0,0 +1,63 @@
+; Show that we know how to translate (floating point) vldr and vstr.
+
+; REQUIRES: allow_dump
+
+; Compile using standalone assembler.
+; RUN: %p2i --filetype=asm -i %s --target=arm32 --args -O2 \
+; RUN:   -reg-use r5,s20,d20 \
+; RUN:   | FileCheck %s --check-prefix=ASM
+
+; Show bytes in assembled standalone code.
+; RUN: %p2i --filetype=asm -i %s --target=arm32 --assemble --disassemble \
+; RUN:   --args -O2 \
+; RUN:   -reg-use r5,s20,d20 \
+; RUN:   | FileCheck %s --check-prefix=DIS
+
+; Compile using integrated assembler.
+; RUN: %p2i --filetype=iasm -i %s --target=arm32 --args -O2 \
+; RUN:   -reg-use r5,s20,d20 \
+; RUN:   | FileCheck %s --check-prefix=IASM
+
+; Show bytes in assembled integrated code.
+; RUN: %p2i --filetype=iasm -i %s --target=arm32 --assemble --disassemble \
+; RUN:   --args -O2 \
+; RUN:   -reg-use r5,s20,d20 \
+; RUN:   | FileCheck %s --check-prefix=DIS
+
+@floatVal = internal global [4 x i8] zeroinitializer, align 4
+
+@doubleVal = internal global [8 x i8] zeroinitializer, align 8
+
+define internal float @testFloat() {
+; ASM-LABEL: testFloat:
+; DIS-LABEL: 00000000 <testFloat>:
+
+entry:
+; ASM: .LtestFloat$entry:
+
+  %vaddr = bitcast [4 x i8]* @floatVal to float*

[Jim Stichnoth, 2016/01/19 23:48:25]

If you want to start with even simpler bitcode, you could probably just 'reg
float 1.0' or with some other nonzero constant.

[Karl, 2016/01/21 17:47:36]

Done.

+  %v = load float, float* %vaddr, align 1
+
+; ASM:  vldr    s20, [r5]
+; DIS:   10:    ed95aa00
+; IASM-NOT: vldr
+
+  ret float %v
+}
+
+define internal double @testDouble() {
+; ASM-LABEL: testDouble:
+; DIS-LABEL: 00000030 <testDouble>:
+
+entry:
+; ASM: .LtestDouble$entry:
+
+  %vaddr = bitcast [8 x i8]* @doubleVal to double*
+  %v = load double, double* %vaddr, align 1
+
+; ASM:  vldr    d20, [r5]
+; DIS:   3c:    edd54b00
+; IASM-NOT: vldr
+
+  ret double %v
+}