Add vdlr{s,d} to the integrated ARM assembler.

src/IceAssemblerARM32.cpp

Index: src/IceAssemblerARM32.cpp
diff --git a/src/IceAssemblerARM32.cpp b/src/IceAssemblerARM32.cpp
index 8586016c9c84f98669c5e521d38ded472c52792b..13ec781a9816ae77937c6d53a79ac18fc86a6b12 100644
--- a/src/IceAssemblerARM32.cpp
+++ b/src/IceAssemblerARM32.cpp
@@ -238,7 +238,8 @@ enum EncodedOperand {
   //
   // ***** OpEncodingMemEx *****
   //
-  // Value=000000000000nnnn0000000000000000 where nnnn=Rn.
+  // Value=00000000U000nnnn00000000xxxxxxxx where nnnn=Rn, xxxxxxxx=abs(Offset),
+  // and U=1 Offset>=0.
   EncodedAsImmRegOffset,
   // Value=0000000pu0w00nnnnttttiiiiiss0mmmm where nnnn is the base register Rn,
   // mmmm is the index register Rm, iiiii is the shift amount, ss is the shift
@@ -2187,6 +2188,47 @@ void AssemblerARM32::vdivd(const Operand *OpDd, const Operand *OpDn,
   emitVFPddd(Cond, VdivdOpcode, Dd, Dn, Dm);
 }
 
+void AssemblerARM32::vldrd(const Operand *OpDd, const Operand *OpAddress,
+                           CondARM32::Cond Cond, const TargetInfo &TInfo) {
+  // VLDR - ARM section A8.8.333, encoding A1.
+  //   vldr<c> <Dd>, [<Rn>{, #+/-<imm>}]
+  //
+  // cccc1101UD01nnnndddd1011iiiiiiii where cccc=Cond, nnnn=Rn, Ddddd=Rd,
+  // iiiiiiii=abs(Opcode), and U=1 if Opcode>=0,
+  // cccc1101ud01nnnndddd1010iiiiiiii.

[Karl, 2016/01/21 17:47:36]

Delete this line (don't duplicate pattern).

Done.

+  constexpr const char *Vldrd = "vldrd";
+  IValueT Dd = encodeDRegister(OpDd, "Dd", Vldrd);
+  assert(CondARM32::isDefined(Cond));
+  IValueT Address;
+  assert(encodeAddress(OpAddress, Address, TInfo) == EncodedAsImmRegOffset);
+  AssemblerBuffer::EnsureCapacity ensured(&Buffer);
+  IValueT Encoding = B27 | B26 | B24 | B20 | B11 | B9 | B8 |
+                     (encodeCondition(Cond) << kConditionShift) |
+                     (getYInRegYXXXX(Dd) << 22) |
+                     (getXXXXInRegYXXXX(Dd) << 12) | Address;
+  emitInst(Encoding);
+}
+
+void AssemblerARM32::vldrs(const Operand *OpSd, const Operand *OpAddress,
+                           CondARM32::Cond Cond, const TargetInfo &TInfo) {
+  // VDLR - ARM section A8.8.333, encoding A2.
+  //   vldr<c> <Sd>, [<Rn>{, #+/-<imm>]]
+  //
+  // cccc1101UD01nnnndddd1010iiiiiiii where cccc=Cond, nnnn=Rn, ddddD=Sd,
+  // iiiiiiii=abs(Opcode), and U=1 if Opcode >= 0;
+  constexpr const char *Vldrs = "vldrs";
+  IValueT Sd = encodeSRegister(OpSd, "Sd", Vldrs);
+  assert(CondARM32::isDefined(Cond));
+  IValueT Address;
+  assert(encodeAddress(OpAddress, Address, TInfo) == EncodedAsImmRegOffset);
+  AssemblerBuffer::EnsureCapacity ensured(&Buffer);
+  IValueT Encoding = B27 | B26 | B24 | B20 | B11 | B9 |
+                     (encodeCondition(Cond) << kConditionShift) |
+                     (getYInRegXXXXY(Sd) << 22) |
+                     (getXXXXInRegXXXXY(Sd) << 12) | Address;
+  emitInst(Encoding);
+}
+
 void AssemblerARM32::vmuls(const Operand *OpSd, const Operand *OpSn,
                            const Operand *OpSm, CondARM32::Cond Cond) {
   // VMUL (floating-point) - ARM section A8.8.351, encoding A2: