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| 1 // Copyright (c) 2013, the Dart project authors. Please see the AUTHORS file | 1 // Copyright (c) 2013, the Dart project authors. Please see the AUTHORS file |
| 2 // for details. All rights reserved. Use of this source code is governed by a | 2 // for details. All rights reserved. Use of this source code is governed by a |
| 3 // BSD-style license that can be found in the LICENSE file. | 3 // BSD-style license that can be found in the LICENSE file. |
| 4 // | 4 // |
| 5 // This is forked from Dart revision df52deea9f25690eb8b66c5995da92b70f7ac1fe | 5 // This is forked from Dart revision df52deea9f25690eb8b66c5995da92b70f7ac1fe |
| 6 // Please update the (git) revision if we merge changes from Dart. | 6 // Please update the (git) revision if we merge changes from Dart. |
| 7 // https://code.google.com/p/dart/wiki/GettingTheSource | 7 // https://code.google.com/p/dart/wiki/GettingTheSource |
| 8 | 8 |
| 9 #include "vm/globals.h" // NOLINT | 9 #include "vm/globals.h" // NOLINT |
| 10 #if defined(TARGET_ARCH_ARM) | 10 #if defined(TARGET_ARCH_ARM) |
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| 737 ASSERT(cond != kNoCondition); | 737 ASSERT(cond != kNoCondition); |
| 738 int32_t encoding = (static_cast<int32_t>(cond) << kConditionShift) | | 738 int32_t encoding = (static_cast<int32_t>(cond) << kConditionShift) | |
| 739 B27 | B26 | B22 | B20 | | 739 B27 | B26 | B22 | B20 | |
| 740 (static_cast<int32_t>(rt2)*B16) | | 740 (static_cast<int32_t>(rt2)*B16) | |
| 741 (static_cast<int32_t>(rt)*B12) | B11 | B9 | B8 | | 741 (static_cast<int32_t>(rt)*B12) | B11 | B9 | B8 | |
| 742 ((static_cast<int32_t>(dm) >> 4)*B5) | B4 | | 742 ((static_cast<int32_t>(dm) >> 4)*B5) | B4 | |
| 743 (static_cast<int32_t>(dm) & 0xf); | 743 (static_cast<int32_t>(dm) & 0xf); |
| 744 Emit(encoding); | 744 Emit(encoding); |
| 745 } | 745 } |
| 746 | 746 |
| 747 | 747 #if 0 |
| 748 // Moved to ARM32::AssemblerARM32::vldrs() |
| 748 void Assembler::vldrs(SRegister sd, Address ad, Condition cond) { | 749 void Assembler::vldrs(SRegister sd, Address ad, Condition cond) { |
| 749 ASSERT(TargetCPUFeatures::vfp_supported()); | 750 ASSERT(TargetCPUFeatures::vfp_supported()); |
| 750 ASSERT(sd != kNoSRegister); | 751 ASSERT(sd != kNoSRegister); |
| 751 ASSERT(cond != kNoCondition); | 752 ASSERT(cond != kNoCondition); |
| 752 int32_t encoding = (static_cast<int32_t>(cond) << kConditionShift) | | 753 int32_t encoding = (static_cast<int32_t>(cond) << kConditionShift) | |
| 753 B27 | B26 | B24 | B20 | | 754 B27 | B26 | B24 | B20 | |
| 754 ((static_cast<int32_t>(sd) & 1)*B22) | | 755 ((static_cast<int32_t>(sd) & 1)*B22) | |
| 755 ((static_cast<int32_t>(sd) >> 1)*B12) | | 756 ((static_cast<int32_t>(sd) >> 1)*B12) | |
| 756 B11 | B9 | ad.vencoding(); | 757 B11 | B9 | ad.vencoding(); |
| 757 Emit(encoding); | 758 Emit(encoding); |
| 758 } | 759 } |
| 759 | 760 #endif |
| 760 | 761 |
| 761 void Assembler::vstrs(SRegister sd, Address ad, Condition cond) { | 762 void Assembler::vstrs(SRegister sd, Address ad, Condition cond) { |
| 762 ASSERT(TargetCPUFeatures::vfp_supported()); | 763 ASSERT(TargetCPUFeatures::vfp_supported()); |
| 763 ASSERT(static_cast<Register>(ad.encoding_ & (0xf << kRnShift)) != PC); | 764 ASSERT(static_cast<Register>(ad.encoding_ & (0xf << kRnShift)) != PC); |
| 764 ASSERT(sd != kNoSRegister); | 765 ASSERT(sd != kNoSRegister); |
| 765 ASSERT(cond != kNoCondition); | 766 ASSERT(cond != kNoCondition); |
| 766 int32_t encoding = (static_cast<int32_t>(cond) << kConditionShift) | | 767 int32_t encoding = (static_cast<int32_t>(cond) << kConditionShift) | |
| 767 B27 | B26 | B24 | | 768 B27 | B26 | B24 | |
| 768 ((static_cast<int32_t>(sd) & 1)*B22) | | 769 ((static_cast<int32_t>(sd) & 1)*B22) | |
| 769 ((static_cast<int32_t>(sd) >> 1)*B12) | | 770 ((static_cast<int32_t>(sd) >> 1)*B12) | |
| 770 B11 | B9 | ad.vencoding(); | 771 B11 | B9 | ad.vencoding(); |
| 771 Emit(encoding); | 772 Emit(encoding); |
| 772 } | 773 } |
| 773 | 774 |
| 774 | 775 #if 0 |
| 776 // Moved to ARM32::AssemblerARM32::vldrd() |
| 775 void Assembler::vldrd(DRegister dd, Address ad, Condition cond) { | 777 void Assembler::vldrd(DRegister dd, Address ad, Condition cond) { |
| 776 ASSERT(TargetCPUFeatures::vfp_supported()); | 778 ASSERT(TargetCPUFeatures::vfp_supported()); |
| 777 ASSERT(dd != kNoDRegister); | 779 ASSERT(dd != kNoDRegister); |
| 778 ASSERT(cond != kNoCondition); | 780 ASSERT(cond != kNoCondition); |
| 779 int32_t encoding = (static_cast<int32_t>(cond) << kConditionShift) | | 781 int32_t encoding = (static_cast<int32_t>(cond) << kConditionShift) | |
| 780 B27 | B26 | B24 | B20 | | 782 B27 | B26 | B24 | B20 | |
| 781 ((static_cast<int32_t>(dd) >> 4)*B22) | | 783 ((static_cast<int32_t>(dd) >> 4)*B22) | |
| 782 ((static_cast<int32_t>(dd) & 0xf)*B12) | | 784 ((static_cast<int32_t>(dd) & 0xf)*B12) | |
| 783 B11 | B9 | B8 | ad.vencoding(); | 785 B11 | B9 | B8 | ad.vencoding(); |
| 784 Emit(encoding); | 786 Emit(encoding); |
| 785 } | 787 } |
| 786 | 788 #endif |
| 787 | 789 |
| 788 void Assembler::vstrd(DRegister dd, Address ad, Condition cond) { | 790 void Assembler::vstrd(DRegister dd, Address ad, Condition cond) { |
| 789 ASSERT(TargetCPUFeatures::vfp_supported()); | 791 ASSERT(TargetCPUFeatures::vfp_supported()); |
| 790 ASSERT(static_cast<Register>(ad.encoding_ & (0xf << kRnShift)) != PC); | 792 ASSERT(static_cast<Register>(ad.encoding_ & (0xf << kRnShift)) != PC); |
| 791 ASSERT(dd != kNoDRegister); | 793 ASSERT(dd != kNoDRegister); |
| 792 ASSERT(cond != kNoCondition); | 794 ASSERT(cond != kNoCondition); |
| 793 int32_t encoding = (static_cast<int32_t>(cond) << kConditionShift) | | 795 int32_t encoding = (static_cast<int32_t>(cond) << kConditionShift) | |
| 794 B27 | B26 | B24 | | 796 B27 | B26 | B24 | |
| 795 ((static_cast<int32_t>(dd) >> 4)*B22) | | 797 ((static_cast<int32_t>(dd) >> 4)*B22) | |
| 796 ((static_cast<int32_t>(dd) & 0xf)*B12) | | 798 ((static_cast<int32_t>(dd) & 0xf)*B12) | |
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| 3690 | 3692 |
| 3691 | 3693 |
| 3692 const char* Assembler::FpuRegisterName(FpuRegister reg) { | 3694 const char* Assembler::FpuRegisterName(FpuRegister reg) { |
| 3693 ASSERT((0 <= reg) && (reg < kNumberOfFpuRegisters)); | 3695 ASSERT((0 <= reg) && (reg < kNumberOfFpuRegisters)); |
| 3694 return fpu_reg_names[reg]; | 3696 return fpu_reg_names[reg]; |
| 3695 } | 3697 } |
| 3696 | 3698 |
| 3697 } // namespace dart | 3699 } // namespace dart |
| 3698 | 3700 |
| 3699 #endif // defined TARGET_ARCH_ARM | 3701 #endif // defined TARGET_ARCH_ARM |
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