[MIPS] Fix memory barriers for atomic operations.

base/atomicops_internals_mips_gcc.h

 // Copyright (c) 2012 The Chromium Authors. All rights reserved.
 // Use of this source code is governed by a BSD-style license that can be
 // found in the LICENSE file.
 
 // This file is an internal atomic implementation, use base/atomicops.h instead.
 //
 // LinuxKernelCmpxchg and Barrier_AtomicIncrement are from Google Gears.
 
 #ifndef BASE_ATOMICOPS_INTERNALS_MIPS_GCC_H_
 #define BASE_ATOMICOPS_INTERNALS_MIPS_GCC_H_
@@ skipping 72 matching lines @@
                        ".set pop\n"
                        : "=&r" (temp), "=&r" (temp2), "=m" (*ptr)
                        : "Ir" (increment), "m" (*ptr)
                        : "memory");
   // temp2 now holds the final value.
   return temp2;
 }
 
 inline Atomic32 Barrier_AtomicIncrement(volatile Atomic32* ptr,
                                         Atomic32 increment) {
-  ATOMICOPS_COMPILER_BARRIER();
+  MemoryBarrier();
   Atomic32 res = NoBarrier_AtomicIncrement(ptr, increment);
-  ATOMICOPS_COMPILER_BARRIER();
+  MemoryBarrier();
   return res;
 }
 
 // "Acquire" operations
 // ensure that no later memory access can be reordered ahead of the operation.
 // "Release" operations ensure that no previous memory access can be reordered
 // after the operation.  "Barrier" operations have both "Acquire" and "Release"
 // semantics.   A MemoryBarrier() has "Barrier" semantics, but does no memory
 // access.
 inline Atomic32 Acquire_CompareAndSwap(volatile Atomic32* ptr,
                                        Atomic32 old_value,
                                        Atomic32 new_value) {
-  ATOMICOPS_COMPILER_BARRIER();
+  MemoryBarrier();

[Dmitry Vyukov, 2013/06/06 08:14:44]

It must be the other way around:
For acquire: memory operation followed by barrier.
For release: memory operation preceded by barrier.

[paul.l..., 2013/06/06 17:07:03]

Done. Thanks for the review!

   Atomic32 res = NoBarrier_CompareAndSwap(ptr, old_value, new_value);
-  ATOMICOPS_COMPILER_BARRIER();
   return res;
 }
 
 inline Atomic32 Release_CompareAndSwap(volatile Atomic32* ptr,
                                        Atomic32 old_value,
                                        Atomic32 new_value) {
-  ATOMICOPS_COMPILER_BARRIER();
   Atomic32 res = NoBarrier_CompareAndSwap(ptr, old_value, new_value);
-  ATOMICOPS_COMPILER_BARRIER();
+  MemoryBarrier();
   return res;
 }
 
 inline void NoBarrier_Store(volatile Atomic32* ptr, Atomic32 value) {
   *ptr = value;
 }
 
 inline void MemoryBarrier() {
   __asm__ __volatile__("sync" : : : "memory");
 }
@@ skipping 22 matching lines @@
   MemoryBarrier();
   return *ptr;
 }
 
 } // namespace base::subtle
 } // namespace base
 
 #undef ATOMICOPS_COMPILER_BARRIER
 
 #endif  // BASE_ATOMICOPS_INTERNALS_MIPS_GCC_H_