Clean up handling of ARM IR instruction "mov".

tests_lit/assembler/arm32/vmov-cast.ll

Index: tests_lit/assembler/arm32/vmov-cast.ll
diff --git a/tests_lit/assembler/arm32/vadd.ll b/tests_lit/assembler/arm32/vmov-cast.ll
similarity index 52%
copy from tests_lit/assembler/arm32/vadd.ll
copy to tests_lit/assembler/arm32/vmov-cast.ll
index b219a71e4a4d12471936f5f08f4358478245ad4a..2fa59d14ee3757b64e773531643e0b4cdf3d9b8d 100644
--- a/tests_lit/assembler/arm32/vadd.ll
+++ b/tests_lit/assembler/arm32/vmov-cast.ll
@@ -1,7 +1,6 @@
-; Show that we know how to translate vadd.
+; Show that we know how to translate vmov for casts.
 
-; NOTE: Restricts S and D registers to ones that will better test S/D
-; register encodings.
+; NOTE: Restricts S register to one that will better test S register encodings.
 
 ; REQUIRES: allow_dump
 
@@ -27,32 +26,20 @@
 ; RUN:   -reg-use s20,s22,d20,d22 \
 ; RUN:   | FileCheck %s --check-prefix=DIS
 
-define internal float @testVaddFloat(float %v1, float %v2) {
-; ASM-LABEL: testVaddFloat:
-; DIS-LABEL: 00000000 <testVaddFloat>:
-; IASM-LABEL: testVaddFloat:
+define internal float @castToFloat(i32 %a) {
+; ASM-LABEL: castToFloat:
+; DIS-LABEL: 00000000 <castToFloat>:
+; IASM-LABEL: castToFloat:
 
 entry:
-  %res = fadd float %v1, %v2
+; ASM: .LcastToFloat$entry:
+; IASM: .LcastToFloat$entry:
 
-; ASM:     vadd.f32        s20, s20, s22
-; DIS:   1c:       ee3aaa0b
-; IASM-NOT:     vadd
+  %0 = bitcast i32 %a to float
 
-  ret float %res
-}
-
-define internal double @testVaddDouble(double %v1, double %v2) {
-; ASM-LABEL: testVaddDouble:
-; DIS-LABEL: 00000040 <testVaddDouble>:
-; IASM-LABEL: .LtestVaddDouble$entry:
-
-entry:
-  %res = fadd double %v1, %v2
-
-; ASM:        vadd.f64        d20, d20, d22
-; DIS:      54:       ee744ba6
-; IASM-NOT:   vadd
+; ASM:          vmov    s20, r0
+; DIS:  10:     ee0a0a10
+; IASM-NOT:     vmov
 
-  ret double %res
+  ret float %0
 }