Clean up handling of ARM IR instruction "mov".

src/IceAssemblerARM32.cpp

Index: src/IceAssemblerARM32.cpp
diff --git a/src/IceAssemblerARM32.cpp b/src/IceAssemblerARM32.cpp
index 8586016c9c84f98669c5e521d38ded472c52792b..95c612fa8bf84219d94414adc4458caaee2e2737 100644
--- a/src/IceAssemblerARM32.cpp
+++ b/src/IceAssemblerARM32.cpp
@@ -196,6 +196,7 @@ IValueT getEncodedGPRegNum(const Variable *Var) {
 }
 
 IValueT getEncodedSRegNum(const Variable *Var) {
+  assert(Var->hasReg());
   return RegARM32::getEncodedSReg(Var->getRegNum());
 }
 
@@ -2187,6 +2188,27 @@ void AssemblerARM32::vdivd(const Operand *OpDd, const Operand *OpDn,
   emitVFPddd(Cond, VdivdOpcode, Dd, Dn, Dm);
 }
 
+void AssemblerARM32::vmovsr(const Operand *OpSn, const Operand *OpRt,
+                            CondARM32::Cond Cond) {
+  // VMOV (between ARM core register and single-precision register)
+  //   ARM seciont A8.8.343, encoding A1.
+  //
+  //   vmov<c> <Sn>, <Rt>
+  //
+  // cccc1110000onnnntttt1010N0010000 where cccc=Cond, nnnnN = Sn, and tttt=Rt.
+  constexpr const char *Vmovsr = "vmovsr";
+  IValueT Sn = encodeSRegister(OpSn, "Sn", Vmovsr);
+  IValueT Rt = encodeGPRegister(OpRt, "Rt", Vmovsr);
+  assert(Sn < RegARM32::getNumSRegs());
+  assert(Rt < RegARM32::getNumGPRegs());
+  assert(CondARM32::isDefined(Cond));
+  AssemblerBuffer::EnsureCapacity ensured(&Buffer);
+  IValueT Encoding = (encodeCondition(Cond) << kConditionShift) | B27 | B26 |
+                     B25 | B11 | B9 | B4 | (getXXXXInRegXXXXY(Sn) << 16) |
+                     (Rt << kRdShift) | (getYInRegXXXXY(Sn) << 7);
+  emitInst(Encoding);
+}
+
 void AssemblerARM32::vmuls(const Operand *OpSd, const Operand *OpSn,
                            const Operand *OpSm, CondARM32::Cond Cond) {
   // VMUL (floating-point) - ARM section A8.8.351, encoding A2: