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Issue 15945006: Fix leaf floating point runtime calls on ARM (work still needed in simulator). (Closed) Base URL: http://dart.googlecode.com/svn/branches/bleeding_edge/dart/
Patch Set: Created 7 years, 6 months ago
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1 // Copyright (c) 2013, the Dart project authors. Please see the AUTHORS file 1 // Copyright (c) 2013, the Dart project authors. Please see the AUTHORS file
2 // for details. All rights reserved. Use of this source code is governed by a 2 // for details. All rights reserved. Use of this source code is governed by a
3 // BSD-style license that can be found in the LICENSE file. 3 // BSD-style license that can be found in the LICENSE file.
4 4
5 #include "vm/globals.h" // Needed here to get TARGET_ARCH_ARM. 5 #include "vm/globals.h" // Needed here to get TARGET_ARCH_ARM.
6 #if defined(TARGET_ARCH_ARM) 6 #if defined(TARGET_ARCH_ARM)
7 7
8 #include "vm/flow_graph_compiler.h" 8 #include "vm/flow_graph_compiler.h"
9 9
10 #include "lib/error.h" 10 #include "lib/error.h"
(...skipping 1622 matching lines...) Expand 10 before | Expand all | Expand 10 after
1633 } else { 1633 } else {
1634 ASSERT(destination.IsQuadStackSlot()); 1634 ASSERT(destination.IsQuadStackSlot());
1635 UNIMPLEMENTED(); 1635 UNIMPLEMENTED();
1636 } 1636 }
1637 } 1637 }
1638 } else if (source.IsDoubleStackSlot()) { 1638 } else if (source.IsDoubleStackSlot()) {
1639 if (destination.IsFpuRegister()) { 1639 if (destination.IsFpuRegister()) {
1640 __ vldrd(destination.fpu_reg(), source.ToStackSlotAddress()); 1640 __ vldrd(destination.fpu_reg(), source.ToStackSlotAddress());
1641 } else { 1641 } else {
1642 ASSERT(destination.IsDoubleStackSlot()); 1642 ASSERT(destination.IsDoubleStackSlot());
1643 __ vldrd(FpuTMP, source.ToStackSlotAddress()); 1643 __ vldrd(DTMP, source.ToStackSlotAddress());
1644 __ vstrd(FpuTMP, destination.ToStackSlotAddress()); 1644 __ vstrd(DTMP, destination.ToStackSlotAddress());
1645 } 1645 }
1646 } else if (source.IsQuadStackSlot()) { 1646 } else if (source.IsQuadStackSlot()) {
1647 UNIMPLEMENTED(); 1647 UNIMPLEMENTED();
1648 } else { 1648 } else {
1649 ASSERT(source.IsConstant()); 1649 ASSERT(source.IsConstant());
1650 if (destination.IsRegister()) { 1650 if (destination.IsRegister()) {
1651 const Object& constant = source.constant(); 1651 const Object& constant = source.constant();
1652 __ LoadObject(destination.reg(), constant); 1652 __ LoadObject(destination.reg(), constant);
1653 } else { 1653 } else {
1654 ASSERT(destination.IsStackSlot()); 1654 ASSERT(destination.IsStackSlot());
(...skipping 16 matching lines...) Expand all
1671 __ mov(IP, ShifterOperand(source.reg())); 1671 __ mov(IP, ShifterOperand(source.reg()));
1672 __ mov(source.reg(), ShifterOperand(destination.reg())); 1672 __ mov(source.reg(), ShifterOperand(destination.reg()));
1673 __ mov(destination.reg(), ShifterOperand(IP)); 1673 __ mov(destination.reg(), ShifterOperand(IP));
1674 } else if (source.IsRegister() && destination.IsStackSlot()) { 1674 } else if (source.IsRegister() && destination.IsStackSlot()) {
1675 Exchange(source.reg(), destination.ToStackSlotAddress()); 1675 Exchange(source.reg(), destination.ToStackSlotAddress());
1676 } else if (source.IsStackSlot() && destination.IsRegister()) { 1676 } else if (source.IsStackSlot() && destination.IsRegister()) {
1677 Exchange(destination.reg(), source.ToStackSlotAddress()); 1677 Exchange(destination.reg(), source.ToStackSlotAddress());
1678 } else if (source.IsStackSlot() && destination.IsStackSlot()) { 1678 } else if (source.IsStackSlot() && destination.IsStackSlot()) {
1679 Exchange(destination.ToStackSlotAddress(), source.ToStackSlotAddress()); 1679 Exchange(destination.ToStackSlotAddress(), source.ToStackSlotAddress());
1680 } else if (source.IsFpuRegister() && destination.IsFpuRegister()) { 1680 } else if (source.IsFpuRegister() && destination.IsFpuRegister()) {
1681 __ vmovd(FpuTMP, source.fpu_reg()); 1681 __ vmovd(DTMP, source.fpu_reg());
1682 __ vmovd(source.fpu_reg(), destination.fpu_reg()); 1682 __ vmovd(source.fpu_reg(), destination.fpu_reg());
1683 __ vmovd(destination.fpu_reg(), FpuTMP); 1683 __ vmovd(destination.fpu_reg(), DTMP);
1684 } else if (source.IsFpuRegister() || destination.IsFpuRegister()) { 1684 } else if (source.IsFpuRegister() || destination.IsFpuRegister()) {
1685 ASSERT(destination.IsDoubleStackSlot() || 1685 ASSERT(destination.IsDoubleStackSlot() ||
1686 destination.IsQuadStackSlot() || 1686 destination.IsQuadStackSlot() ||
1687 source.IsDoubleStackSlot() || 1687 source.IsDoubleStackSlot() ||
1688 source.IsQuadStackSlot()); 1688 source.IsQuadStackSlot());
1689 bool double_width = destination.IsDoubleStackSlot() || 1689 bool double_width = destination.IsDoubleStackSlot() ||
1690 source.IsDoubleStackSlot(); 1690 source.IsDoubleStackSlot();
1691 DRegister reg = source.IsFpuRegister() ? source.fpu_reg() 1691 DRegister reg = source.IsFpuRegister() ? source.fpu_reg()
1692 : destination.fpu_reg(); 1692 : destination.fpu_reg();
1693 const Address& slot_address = source.IsFpuRegister() 1693 const Address& slot_address = source.IsFpuRegister()
1694 ? destination.ToStackSlotAddress() 1694 ? destination.ToStackSlotAddress()
1695 : source.ToStackSlotAddress(); 1695 : source.ToStackSlotAddress();
1696 1696
1697 if (double_width) { 1697 if (double_width) {
1698 __ vldrd(FpuTMP, slot_address); 1698 __ vldrd(DTMP, slot_address);
1699 __ vstrd(reg, slot_address); 1699 __ vstrd(reg, slot_address);
1700 __ vmovd(reg, FpuTMP); 1700 __ vmovd(reg, DTMP);
1701 } else { 1701 } else {
1702 UNIMPLEMENTED(); 1702 UNIMPLEMENTED();
1703 } 1703 }
1704 } else if (source.IsDoubleStackSlot() && destination.IsDoubleStackSlot()) { 1704 } else if (source.IsDoubleStackSlot() && destination.IsDoubleStackSlot()) {
1705 const Address& source_slot_address = source.ToStackSlotAddress(); 1705 const Address& source_slot_address = source.ToStackSlotAddress();
1706 const Address& destination_slot_address = destination.ToStackSlotAddress(); 1706 const Address& destination_slot_address = destination.ToStackSlotAddress();
1707 1707
1708 ScratchFpuRegisterScope ensure_scratch(this, FpuTMP); 1708 ScratchFpuRegisterScope ensure_scratch(this, DTMP);
1709 __ vldrd(FpuTMP, source_slot_address); 1709 __ vldrd(DTMP, source_slot_address);
1710 __ vldrd(ensure_scratch.reg(), destination_slot_address); 1710 __ vldrd(ensure_scratch.reg(), destination_slot_address);
1711 __ vstrd(FpuTMP, destination_slot_address); 1711 __ vstrd(DTMP, destination_slot_address);
1712 __ vstrd(ensure_scratch.reg(), source_slot_address); 1712 __ vstrd(ensure_scratch.reg(), source_slot_address);
1713 } else if (source.IsQuadStackSlot() && destination.IsQuadStackSlot()) { 1713 } else if (source.IsQuadStackSlot() && destination.IsQuadStackSlot()) {
1714 UNIMPLEMENTED(); 1714 UNIMPLEMENTED();
1715 } else { 1715 } else {
1716 UNREACHABLE(); 1716 UNREACHABLE();
1717 } 1717 }
1718 1718
1719 // The swap of source and destination has executed a move from source to 1719 // The swap of source and destination has executed a move from source to
1720 // destination. 1720 // destination.
1721 move->Eliminate(); 1721 move->Eliminate();
(...skipping 60 matching lines...) Expand 10 before | Expand all | Expand 10 after
1782 void ParallelMoveResolver::RestoreFpuScratch(FpuRegister reg) { 1782 void ParallelMoveResolver::RestoreFpuScratch(FpuRegister reg) {
1783 __ vldrd(reg, Address(SP, kDoubleSize, Address::PostIndex)); 1783 __ vldrd(reg, Address(SP, kDoubleSize, Address::PostIndex));
1784 } 1784 }
1785 1785
1786 1786
1787 #undef __ 1787 #undef __
1788 1788
1789 } // namespace dart 1789 } // namespace dart
1790 1790
1791 #endif // defined TARGET_ARCH_ARM 1791 #endif // defined TARGET_ARCH_ARM
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