MIPS: Refine 'r6 compact branch optimization.'

src/mips/disasm-mips.cc

 // Copyright 2012 the V8 project authors. All rights reserved.
 // Use of this source code is governed by a BSD-style license that can be
 // found in the LICENSE file.
 
 // A Disassembler object is used to disassemble a block of code instruction by
 // instruction. The default implementation of the NameConverter object can be
 // overriden to modify register names or to do symbol lookup on addresses.
 //
 // The example below will disassemble a block of code and print it to stdout.
 //
@@ skipping 1482 matching lines @@
     case ADDI:
       if (!IsMipsArchVariant(kMips32r6)) {
         Format(instr, "addi    'rt, 'rs, 'imm16s");
       } else {
         int rs_reg = instr->RsValue();
         int rt_reg = instr->RtValue();
         // Check if BOVC, BEQZALC or BEQC instruction.
         if (rs_reg >= rt_reg) {
           Format(instr, "bovc  'rs, 'rt, 'imm16s -> 'imm16p4s2");
         } else {
+          DCHECK(rt_reg > 0);
           if (rs_reg == 0) {
             Format(instr, "beqzalc 'rt, 'imm16s -> 'imm16p4s2");
           } else {
             Format(instr, "beqc    'rs, 'rt, 'imm16s -> 'imm16p4s2");
           }
         }
       }
       break;
     case DADDI:
       if (IsMipsArchVariant(kMips32r6)) {
         int rs_reg = instr->RsValue();
         int rt_reg = instr->RtValue();
         // Check if BNVC, BNEZALC or BNEC instruction.
         if (rs_reg >= rt_reg) {
           Format(instr, "bnvc  'rs, 'rt, 'imm16s -> 'imm16p4s2");
         } else {
+          DCHECK(rt_reg > 0);
           if (rs_reg == 0) {
             Format(instr, "bnezalc 'rt, 'imm16s -> 'imm16p4s2");
           } else {
             Format(instr, "bnec  'rs, 'rt, 'imm16s -> 'imm16p4s2");
           }
         }
       }
       break;
     case ADDIU:
       Format(instr, "addiu   'rt, 'rs, 'imm16s");
@@ skipping 232 matching lines @@
         prev_pc, *reinterpret_cast<int32_t*>(prev_pc), buffer.start());
   }
 }
 
 
 #undef UNSUPPORTED
 
 }  // namespace disasm
 
 #endif  // V8_TARGET_ARCH_MIPS